OBSOLETE
1, 2, 4 MEG x 64
NONBUFFERED DRAM DIMMs
DRAM
MODULE
FEATURES
• JEDEC pinout in a 168-pin, dual in-line memory
module (DIMM)
• 8MB (1 Meg x 64), 16MB (2 Meg x 64) and
32MB (4 Meg x 64)
• Nonbuffered
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V
power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• FAST-PAGE-MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
[MT4LD(T)164A(X)]
2,048-cycle refresh (11 row, 10 column addresses)
[MT8LD264A(X)]
2,048-cycle refresh (11 row, 11 column addresses)
[MT16LD464A(X)]
• Serial presence-detect (SPD)
MT4LDT164A(X), MT8LD264A(X),
MT16LD464A(X)
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Front View)
168-Pin DIMM
OPTIONS
• Components
SOJ
TSOP (1 Meg x 64 only)
• Package
168-pin DIMM (gold)
• Timing
50ns access
60ns access
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
*EDO version only
MARKING
D
DT
G
-5*
-6
None
X
NOTE:
Pin symbols in parentheses are not used on these modules but may be used
for other modules in this product family. They are for reference only.
PIN SYMBOL
PIN
1
V
SS
43
2
DQ0
44
3
DQ1
45
4
DQ2
46
5
DQ3
47
6
V
DD
48
7
DQ4
49
8
DQ5
50
9
DQ6
51
10
DQ7
52
11
DQ8
53
12
V
SS
54
13
DQ9
55
14
DQ10
56
15
DQ11
57
16
DQ12
58
17
DQ13
59
18
V
DD
60
19
DQ14
61
20
DQ15
62
21
NC
63
22
NC
64
23
V
SS
65
24
NC
66
25
NC
67
26
V
DD
68
27
WE0#
69
28
CAS0#
70
29
CAS1#
71
30
RAS0#
72
31
OE0#
73
32
V
SS
74
33
A0
75
34
A2
76
35
A4
77
36
A6
78
37
A8
79
38
NC**/A10
80
39
NC (A12)
81
40
V
DD
82
41
V
DD
83
42
RFU
84
**1 Meg x 64 version only
SYMBOL
V
SS
OE2#
RAS2#
CAS2#
CAS3#
WE2#
V
DD
NC
NC
NC
NC
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
NC
RFU
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
NC
NC
NC
SDA
SCL
V
DD
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
NC
NC
V
SS
NC
NC
V
DD
RFU
CAS4#
CAS5#
NC
RFU
V
SS
A1
A3
A5
A7
A9
NC (A11)
NC (A13)
V
DD
RFU
RFU
PIN
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
V
SS
RFU
NC
CAS6#
CAS7#
RFU
V
DD
NC
NC
NC
NC
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
NC
RFU
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
NC
NC
SA0
SA1
SA2
V
DD
1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs
DM67.p65 – Rev. 6/98
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
OBSOLETE
1, 2, 4 MEG x 64
NONBUFFERED DRAM DIMMs
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13/15ns* 8ns
15
10ns
by a column address strobed in by CAS#. Additional col-
umns may be accessed by providing valid column
addresses, strobing CAS# and holding RAS# LOW , thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST-PAGE-MODE operation.
*8MB DIMM
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version, is an
accelerated FAST-PAGE-MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of CAS# output control provides for pipeline
READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO-PAGE-MODE DRAMs operate like FAST-
PAGE-MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing WE# to the idle banks during CAS# HIGH
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after
t
OFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last. (Refer to the 4 Meg x 4 (MT4LC4M4E8) DRAM
data sheet for additional information on EDO functional-
ity.)
FPM Operating Mode
SPEED
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
110ns
60ns
35ns
30ns
15ns
40ns
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT4LDT164AG-5 X
MT4LDT164AG-6 X
MT8LD264AG-5 X
MT8LD264AG-6 X
MT16LD464AG-5 X
MT16LD464AG-6 X
CONFIGURATION
1 Meg x 64
1 Meg x 64
2 Meg x 64
2 Meg x 64
4 Meg x 64
4 Meg x 64
SPEED
50ns
60ns
50ns
60ns
50ns
60ns
PACKAGE
TSOP
TSOP
SOJ
SOJ
SOJ
SOJ
FPM Operating Mode
PART NUMBER
MT4LDT164AG-6
MT8LD264AG-6
MT16LD464AG-6
CONFIGURATION
1 Meg x 64
2 Meg x 64
4 Meg x 64
SPEED
60ns
60ns
60ns
PACKAGE
TSOP
SOJ
SOJ
GENERAL DESCRIPTION
The MT4LDT164A(X), MT8LD264A(X) and
MT16LD464A(X) are randomly accessed 8MB, 16MB and
32MB memories organized in a x64 configuration. During
READ or WRITE cycles, each bit is uniquely addressed
through the 20/21/22 address bits, which are entered 10/
11 bits (A0 -A10) at RAS# time and 10/11 bits (A0-A10) at
CAS# time.
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-detect
(SPD). The SPD function is implemented using a 2,048-bit
EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to
identify the module type and various DRAM organizations
and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/
WRITE operations between the master (system logic) and
the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
page boundary. The FAST-PAGE-MODE cycle is always
initiated with a row address strobed in by RAS#, followed
1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs
DM67.p65 – Rev. 6/98
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
OBSOLETE
1, 2, 4 MEG x 64
NONBUFFERED DRAM DIMMs
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved
for indicating start and stop conditions (Figures 1 and 2).
SPD START CONDITION
All commands are preceded by the start condition, which
is a HIGH-to-LOW transition of SDA when SCL is HIGH.
The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met.
SPD STOP CONDITION
All communications are terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the SPD
device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data (Figure 3).
The SPD device will always respond with an acknowl-
edge after recognition of a start condition and its slave
address. If both the device and a write operation have been
selected, the SPD device will respond with an acknowledge
after the receipt of each subsequent eight-bit word. In the
read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition
is generated by the master, the slave will continue to trans-
mit data. If an acknowledge is not detected, the slave will
terminate further data transmissions and await the stop
condition to return to standby power mode.
SCL
SCL
SDA
DATA STABLE
DATA
CHANGE
DATA STABLE
SDA
START
BIT
STOP
BIT
Figure 1
DATA VALIDITY
Figure 2
DEFINITION OF START AND STOP
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Figure 3
ACKNOWLEDGE RESPONSE FROM RECEIVER
1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs
DM67.p65 – Rev. 6/98
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
OBSOLETE
1, 2, 4 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT4LDT164A(X) (8MB)
DQ0-DQ15
DQ16-DQ31
16
16
DQ0-DQ15
DQ0-DQ15
WE#
U2
OE#
RAS#
LCAS#
WE0#
OE0#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
A0-A9
WE#
U1
OE#
RAS#
LCAS#
UCAS#
A0–A9
UCAS#
A0–A9
10
10
DQ32-DQ47
10
DQ48-DQ63
16
16
DQ0-DQ15
DQ0-DQ15
WE#
U4
OE#
RAS#
LCAS#
WE2#
OE2#
RAS2#
CAS4#
CAS5#
CAS6#
CAS7#
WE#
U3
OE#
RAS#
LCAS#
UCAS#
A0–A9
UCAS#
A0–A9
10
10
SPD
SCL
A0
SA0
A1
SA1
A2
SA2
SDA
U1-U4 = MT4LC1M16C3 FAST PAGE MODE
U1-U4 = MT4LC1M16E5 EDO PAGE MODE
V
DD
V
SS
U1-U4
U1-U4
1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs
DM67.p65 – Rev. 6/98
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
OBSOLETE
1, 2, 4 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT8LD264A(X) (16MB)
DQ0-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
WE0#
OE0#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
A0-A10
11
DQ0-DQ7
WE#
U1
OE#
RAS#
CAS# A0–A10
11
DQ0-DQ7
WE#
U2
OE#
RAS#
CAS# A0–A10
11
DQ0-DQ7
WE#
U3
OE#
RAS#
CAS# A0–A10
11
DQ0-DQ7
WE#
U4
OE#
RAS#
CAS# A0–A10
11
DQ32-DQ39
DQ40-DQ47
DQ48-DQ55
DQ56-DQ63
WE2#
OE2#
RAS2#
CAS4#
CAS5#
CAS6#
CAS7#
DQ0-DQ7
WE#
U5
OE#
RAS#
CAS# A0–A10
11
DQ0-DQ7
WE#
U6
OE#
RAS#
CAS# A0–A10
11
DQ0-DQ7
WE#
U7
OE#
RAS#
CAS# A0–A10
11
DQ0-DQ7
WE#
U8
OE#
RAS#
CAS# A0–A10
11
SPD
SCL
A0
A1
A2
SA0 SA1 SA2
SDA
V
DD
V
SS
U1-U8
U1-U8
U1-U8 = MT4LC2M8B1 FAST PAGE MODE
U1-U8 = MT4LC2M8E7 EDO PAGE MODE
FUNCTIONAL BLOCK DIAGRAM
MT16LD464A(X) (32MB)
DQ0-DQ3
DQ4-DQ7
DQ8-DQ11
DQ12-DQ15
DQ16-DQ19
DQ20-DQ23
DQ24-DQ27
DQ28-DQ31
DQ0-DQ3
DQ0-DQ3
WE#
U2
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U3
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U4
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U5
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U6
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U7
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U8
OE#
RAS#
CAS# A0–A10
WE0#
OE0#
RAS0#
CAS0#
CAS1#
CAS2#
CAS3#
A0-A10
11
WE#
U1
OE#
RAS#
CAS# A0–A10
11
11
11
11
11
11
11
11
DQ32-DQ35
DQ36-DQ39
DQ40-DQ43
DQ44-DQ47
DQ48-DQ51
DQ52-DQ55
DQ56-DQ59
DQ60-DQ63
DQ0-DQ3
DQ0-DQ3
WE#
U10
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U11
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U12
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U13
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U14
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U15
OE#
RAS#
CAS# A0–A10
DQ0-DQ3
WE#
U16
OE#
RAS#
CAS# A0–A10
WE2#
OE2#
RAS2#
CAS4#
CAS5#
CAS6#
CAS7#
WE#
U9
OE#
RAS#
CAS# A0–A10
11
11
11
11
11
11
11
11
SPD
SCL
A0
A1
A2
SA0 SA1 SA2
SDA
U1-U16 = MT4LC4M4B1 FAST PAGE MODE
V
DD
V
SS
U1-U16
U1-U16
U1-U16 = MT4LC4M4E8 EDO PAGE MODE
1, 2, 4 Meg x 64 Nonbuffered DRAM DIMMs
DM67.p65 – Rev. 6/98
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998,
Micron Technology, Inc.
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