K4S511533F - Y(P)C/L/F
8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
FEATURES
• 3.0V & 3.3V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
•
•
•
•
64ms refresh period (8K cycle).
Commercial Temperature Operation (-25°C ~ 70°C).
2 /CS Support.
2Chips DDP 54Balls FBGA( -YXXX -Pb, -PXXX -Pb Free).
Mobile SDRAM
GENERAL DESCRIPTION
The K4S511533F is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
Part No.
K4S511533F-Y(P)C/L/F75
K4S511533F-Y(P)C/L/F1H
K4S511533F-Y(P)C/L/F1L
Max Freq.
133MHz(CL3), 111MHz(CL2)
111MHz(CL2)
111MHz(CL=3)*1, 83MHz(CL2)
LVCMOS
54 FBGA Pb
(Pb Free)
Interface
Package
- Y(P)C/L/F : Normal / Low Power, Commercial Temperature(-25°C ~ 70°C)
NOTES :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur
pose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
Address configuration
Organization
32M x16
Bank
BA0,BA1
Row
A0 - A12
Column Address
A0 - A8
1
September 2004
K4S511533F - Y(P)C/L/F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
ss
Voltage on V
DD
supply relative to V
ss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1.0
50
Mobile SDRAM
Unit
V
V
°C
W
mA
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 70°C)
Parameter
Supply voltage
V
DDQ
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
NOTES :
Symbol
V
DD
Min
2.7
2.7
2.2
-0.3
2.4
-
-2
Typ
3.0
3.0
3.0
0
-
-
-
Max
3.6
3.6
V
DDQ
+ 0.3
0.5
-
0.4
2
Unit
V
V
V
V
V
V
uA
Note
V
IH
V
IL
V
OH
V
OL
I
LI
1
2
I
OH
= -2mA
I
OL
= 2mA
3
1. VIH (max) = 5.3V AC.The overshoot voltage duration is
≤
3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
VIN
≤
VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V
≤
VOUT
≤
VDDQ.
CAPACITANCE
(V
DD
= 2.5V,
Pin
Clock
RAS, CAS, WE, CKE
CS
DQM
Address
DQ
0
~ DQ
15
T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Symbol
C
CLK
C
IN
C
IN
C
IN
C
ADD
C
OUT
Min
3.0
3.0
1.5
3.0
3.0
6.0
Max
6.0
6.0
3.0
6.0
6.0
10.0
Unit
pF
pF
pF
pF
pF
pF
Note
4
September 2004
K4S511533F - Y(P)C/L/F
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25 to 70°C)
Mobile SDRAM
Version
Parameter
Symbol
Test Condition
-75
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
-1H
-1L
Unit
Note
I
CC1
70
70
65
mA
1
I
CC2
P
1.0
mA
1.0
20
mA
10
8
mA
4
45
mA
I
CC2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
Precharge Standby Current
in non power-down mode
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
NS
Input signals are stable
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 10ns
Active Standby Current
in power-down mode
I
CC3
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
-C
-L
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NS
30
mA
Operating Current
(Burst Mode)
I
CC
4
110
100
100
mA
1
Refresh Current
I
CC
5
160
150
1500
130
mA
uA
2
4
5
1200
Max 40
900
800
700
Max 70
1200
900
800
uA
°C
Self Refresh Current
I
CC
6
CKE
≤
0.2V
-F
Internal TCSR
Full Array
1/2 of Full Array
1/4 of Full Array
3
6
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Internal TCSR can be supported(In commercial Temp : Max 40°C/Max 70°C).
4. K4S511633F-Y(P)C**
5. K4S511633F-Y(P)L**
6. K4S511633F-Y(P)F**
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
5
September 2004
FPGA/CPLD
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