DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA2750GR
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
The
µ
PA2750GR is N-Channel MOS Field Effect Transistor
designed for DC/DC converters and power management
application of notebook computers.
PACKAGE DRAWING (Unit: mm)
8
5
1 ; Source 1
2 ; Gate 1
7, 8 ; Drain 1
3 ; Source 2
4 ; Gate 2
5, 6 ; Drain 2
1
4
5.37 Max.
+0.10
–0.05
FEATURES
•
Dual chip type
•
Low on-state resistance
R
DS(on)1
= 15.5 mΩ MAX. (V
GS
= 10 V, I
D
= 4.5 A)
R
DS(on)2
= 21.0 mΩ MAX. (V
GS
= 4.5 V, I
D
= 4.5 A)
R
DS(on)3
= 23.9 mΩ MAX. (V
GS
= 4.0 V, I
D
= 4.5 A)
•
Low C
iss
: C
iss
= 1040 pF TYP. (V
DS
= 10 V, V
GS
= 0 V)
•
Built-in G-S protection diode
•
Small and surface mount package (Power SOP8)
6.0 ±0.3
4.4
0.8
1.8 Max.
1.44
0.15
0.05 Min.
0.5 ±0.2
0.10
1.27
0.40
0.78 Max.
0.12 M
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power SOP8
+0.10
–0.05
µ
PA2750GR
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
Note2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
P
T
T
ch
T
stg
30
±20
±9.0
±36
1.7
2.0
150
–55 to +150
9.0
8.1
V
V
A
A
W
W
°C
°C
A
mJ
Gate
Body
Diode
EQUIVALENT CIRCUIT
(1/2 circuit)
Drain
Total Power Dissipation (1 unit)
Total Power Dissipation (2 unit)
Channel Temperature
Storage Temperature
Single Avalanche Current
Single Avalanche Energy
Note3
Note3
I
AS
E
AS
Gate
Protection
Diode
Source
Notes 1.
PW
≤
10
µ
s, Duty cycle
≤
1%
2
2.
T
A
= 25°C, Mounted on ceramic substrate of 2000 mm x 2.2 mm
3.
Starting T
ch
= 25°C, V
DD
= 15 V, R
G
= 25
Ω,
V
GS
= 20
→
0 V
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
G15780EJ1V0DS00 (1st edition)
Date Published March 2002 NS CP(K)
Printed in Japan
©
2001
µ
PA2750GR
ELECTRICAL CHARACTERISTICS (T
A
= 25°C, All terminals are connected.)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
SYMBOL
I
DSS
I
GSS
V
GS(off)
| y
fs
|
R
DS(on)1
R
DS(on)2
R
DS(on)3
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
V
DD
= 24 V
V
GS
= 10 V
I
D
= 9.0 A
I
F
= 9.0 A, V
GS
= 0 V
I
F
= 9.0 A, V
GS
= 0 V
di/dt = 100 A/
µ
s
TEST CONDITIONS
V
DS
= 30 V, V
GS
= 0 V
V
GS
= ±20 V, V
DS
= 0 V
V
DS
= 10 V, I
D
= 1 mA
V
DS
= 10 V, I
D
= 4.5 A
V
GS
= 10 V, I
D
= 4.5 A
V
GS
= 4.5 V, I
D
= 4.5 A
V
GS
= 4.0 V, I
D
= 4.5 A
V
DS
= 10 V
V
GS
= 0 V
f = 1 MHz
V
DD
= 15 V, I
D
= 4.5 A
V
GS
= 10 V
R
G
= 10
Ω
1.5
5
2.0
11
12.5
16.0
17.9
1040
390
130
13
10
43
9
21
3.3
5.1
0.84
34
34
15.5
21.0
23.9
MIN.
TYP.
MAX.
10
±10
2.5
UNIT
µ
A
µ
A
V
S
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
R
G
= 25
Ω
PG.
V
GS
= 20
→
0 V
50
Ω
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
V
DD
PG.
R
G
V
GS
R
L
V
DD
V
DS
90%
90%
10%
10%
V
GS
Wave Form
0
10%
V
GS
90%
BV
DSS
I
AS
I
D
V
DD
V
DS
V
GS
0
τ
τ
= 1
µs
Duty Cycle
≤
1%
V
DS
V
DS
Wave Form
0
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= 2 mA
PG.
50
Ω
R
L
V
DD
2
Data Sheet G15780EJ1V0DS
µ
PA2750GR
TYPICAL CHARACTERISTICS (T
A
= 25°C)
FORWARD TRANSFER CHARACTERISTICS
100
Pulsed
V
DS
= 10 V
40
4.5 V
35
30
25
20
15
10
5
0.01
0
1
2
3
4
5
0
0
Pulsed
0.2
0.4
0.6
0.8
V
DS
- Drain to Source Voltage - V
1.0
V
GS
= 10 V
4V
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
I
D
- Drain Current - A
1
0.1
T
A
=
−25˚C
25˚C
75˚C
150˚C
V
GS
- Gate to Source Voltage - V
I
D
- Drain Current - A
R
DS(on)
- Drain to Source On-state Resistance - mΩ
10
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
| y
fs
| - Forward Transfer Admittance - S
100
V
DS
= 10 V
Pulsed
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
50
Pulsed
40
I
D
= 9.0 A
30
4.5 A
10
T
A
= 150˚C
75˚C
25˚C
−25˚C
20
1
10
0.1
0.01
0.1
0
1
10
100
0
5
10
15
20
I
D
- Drain Current - A
V
GS
- Gate to Source Voltage - V
R
DS(on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
80
Pulsed
3.0
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
V
DS
= 10 V
I
D
= 1 mA
V
GS(off)
- Gate Cut-off Voltage - V
2.5
2.0
1.5
1.0
0.5
0
−75 −50 −25
60
40
20
V
GS
= 4 V
10 V
4.5 V
0
0.1
1
10
100
0
25
50
75 100 125 150 175
I
D
- Drain Current - A
T
ch
- Channel Temperature - ˚C
Data Sheet G15780EJ1V0DS
3
µ
PA2750GR
R
DS(on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
40
Pulsed
I
D
= 4.5 A
100
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
V
GS
= 10 V
I
SD
- Diode Forward Current - A
4V
10
0V
30
V
GS
= 4 V
20
4.5 V
1
10
10 V
0.1
0
−50 −25
0
25
50
75
100 125 150 175
0.01
0
0.5
1.0
Pulsed
1.5
V
SD
- Source to Drain Voltage - V
T
ch
- Channel Temperature - ˚C
CAPACITANCE vs.
DRAIN TO SOURCE VOLTAGE
10000
1000
SWITCHING CHARACTERISTICS
t
d(on)
, t
r
, t
d(off)
, t
f
- Switching Time - ns
C
iss
, C
oss
, C
rss
- Capacitance - pF
100
t
r
t
d(off)
t
d(on)
1000
C
iss
C
oss
10
t
f
1
V
DD
= 15 V
V
GS
= 10 V
R
G
= 10
Ω
1
10
100
I
D
- Drain Current - A
100
C
rss
V
GS
= 0 V
f = 1 MHz
1
10
100
10
0.1
0.1
0.1
V
DS
- Drain to Source Voltage - V
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
1000
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
35
V
DS
- Drain to Source Voltage - V
t
rr
- Reverse Recovery Time - ns
30
25
20
15
10
5
0
0
2
4
6
8
Q
G
- Gate Charge - nC
V
DS
I
D
= 9 A
V
DD
= 24 V
15 V
6V
V
GS
12
10
8
6
4
2
0
100
10
1
0.1
1
10
100
10 12 14 16 18 20 22
I
F
- Drain Current - A
4
Data Sheet G15780EJ1V0DS
V
GS
- Gate to Source Voltage - V
di/dt = 100 A/
µ
s
V
GS
= 0 V
14
µ
PA2750GR
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
P
T
- Total Power Dissipation - W/package
120
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
0
20
40
60
80
100 120 140 160
T
A
- Ambient Temperature - ˚C
2 unit
1 unit
Mounted on ceramic
substrate of
2000 mm
2
×
2.2 mm
dT - Percentage of Rated Power - %
100
80
60
40
20
0
0
20
40
60
80
100 120 140 160
T
A
- Ambient Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
100
d
ite
Lim V)
)
on
10
S(
R
D GS
=
V
(
I
D(DC)
I
D(pulse)
PW
=1
00
s
I
D
- Drain Current - A
10
1m
µ
s
10
Po
we
r
ms
10
Di
ss
ipa
0m
1
s
tio
nL
im
ite
d
0.1
Mounted on
2
ceramic substrate
of 2000 mm x 2.2 mm
Single Pulse, 1 unit
T
A
= 25˚C
Single Pulse
0.01
0.1
1
10
100
V
DS
- Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
r
th(t)
- Transient Thermal Resistance - ˚C/W
1000
Mounted on ceramic substrate
2
of 2000 mm x 2.2 mm
Single Pulse, 1 unit
T
A
= 25˚C
100
R
th(ch-A)
= 73.5˚C/W
10
1
0.1
0.0001
0.001
0.01
0.1
1
10
100
1000
PW - Pulse Width - s
Data Sheet G15780EJ1V0DS
5
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