W3H64M72E-533ESC datasheet, PDF

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W3H64M72E-533ESC: DescriptionDDR DRAM, 64MX72, 0.5ns, CMOS, PBGA208, 17 X 23 MM, 1 MM PITCH, PLASTIC, BGA-208; Categorystorage storage; File Size1000KB，30 Pages; ManufacturerMercury Systems Inc

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W3H64M72E-533ESC Overview

DDR DRAM, 64MX72, 0.5ns, CMOS, PBGA208, 17 X 23 MM, 1 MM PITCH, PLASTIC, BGA-208

W3H64M72E-533ESC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Mercury Systems Inc
package instruction	BGA,
Reach Compliance Code	compliant
access mode	MULTI BANK PAGE BURST
Maximum access time	0.5 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B208
memory density	4831838208 bit
Memory IC Type	DDR DRAM
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	208
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX72
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED

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White Electronic Designs

W3H64M72E-XSBX

ADVANCED*

64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

FEATURES

Data rate = 667*, 533, 400

Package:

• 208 Plastic Ball Grid Array (PBGA), 17 x 23mm

• 1.0mm pitch

DDR2 Data Rate = 667*, 533, 400

Core Supply Voltage = 1.8V ± 0.1V

I/O Supply Voltage = 1.8V ± 0.1V - (SSTL_18

compatible)

Differential data strobe (DQS, DQS#) per byte

Internal, pipelined, double data rate architecture

4-bit prefetch architecture

DLL for alignment of DQ and DQS transitions with

clock signal

Eight internal banks for concurrent operation

(Per DDR2 SDRAM Die)

Programmable Burst lengths: 4 or 8

Auto Refresh and Self Refresh Modes

On Die Termination (ODT)

Adjustable data – output drive strength

Programmable CAS latency: 3, 4 or 5

Posted CAS additive latency: 0, 1, 2, 3 or 4

Write latency = Read latency - 1*

Commercial, Industrial and Military Temperature

Ranges

Organized as 64M x 72

Weight: W3H64M72E-XSBX - 2.5 grams typical

BENEFITS

63% SPACE SAVINGS vs. FPBGA

Reduced part count

55% I/O reduction vs FPBGA

Reduced trace lengths for lower parasitic

capacitance

Suitable for hi-reliability applications

Upgradable to 128M x 72 density (contact factory

for information)

* This product is under development, is not qualiﬁed or characterized and is subject

to change or cancellation without notice.

FIGURE 1 – DENSITY COMPARISONS

Actual Size

W3H64M72E-XSBX

11.0

CSP Approach (mm)

11.0

19.0

FBGA

White Electronic Designs

W3H64M72E-XSBX

63%

55%

Area

I/O

Count

5 x 209mm

= 1,045mm

5 x 92 balls = 460 balls

391mm

208 Balls

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

December 2006

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

TABLE 1 – BALL DESCRIPTIONS

Symbol

ODT

Type

Input

Description

W3H64M72E-XSBX

ADVANCED*

On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When

enabled, ODT is only applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and

UDQS#. The ODT input will be ignored if disabled via the LOAD MODE command.

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing

of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the

crossings of CK and CK#.

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the

DDR2 SDRAM. The speciﬁc circuitry that is enabled/disabled is dependent on the DDR2 SDRAM conﬁguration

and operating mode. CKE LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks

idle), or ACTIVE power-down (row active in any bank). CKE is synchronous for power-down entry, Power-down

exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding

CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh.

CKE is an SSTL_18 input but will detect a LVCMO SLOW level once V

is applied during

ﬁ

rst power-up. After

REF

has become stable during the power on and initialization sequence, it must be maintained for proper

operation of the CKE receiver. For proper SELF-REFRESH operation, V

REF

must be maintained.

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands

are masked when CS# is registered HIGH.

Command inputs: RAS#, CAS#, WE# (along with CS#) deﬁne the command being entered.

Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled

HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM

loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for

upper byte DQ8–DQ15, of each of U0-U4

Bank address inputs: BA0–BA2 deﬁne to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is

being applied. BA0–BA2 deﬁne which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the

LOAD MODE command.

Continued on next page

CK, CK#

Input

CKE

Input

CS#

RAS#, CAS#,

WE#

LDM, UDM

Input

BA0–BA2

Input

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

December 2006

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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