T6A04A
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6A04A
Column and Row Driver LSI for a Dot Matrix Graphic LCD
The T6A04A is a driver for a small-to-medium-sized scale dot
matrix graphic LCD. It includes the functions of the T9841B
(column driver) and the T9842B (row driver). It has an 8-bit
interface circuit and can be operated with an 80-Series MPU. It
generates all the timing signals for the display with an on-chip
oscillator. It receives 8-bit data from an MPU, latches the data to
an on-chip RAM, and displays the image on the LCD (the data in
the display RAM correspond to the dots on the display). The
device has 120 column driver outputs and 64 row driver outputs
enabling it to drive a 120-dot by 64-dot LCD. In addition, there
are resistors to divide the bias voltage, a power supply op-amp,
DC-DC converter (+5 V
→−5
V) and contrast control circuit,
enabling the LCD to be driven by a single power supply. The
device can be connected to another T6A04A to drive a 240-dot by
64-dot LCD.
Unit: mm
T6A04A
(UAW, 6NS)
(UEM, 7NS)
Lead Pitch
IN
1.0
0.4
OUT
0.28
0.4
Please contact Toshiba or an authorized
Toshiba dealer for information on package
dimensions.
TCP (Tape Carrier Package)
Features
•
•
On-chip display RAM capacity
Display RAM data
(1) Display data = 1 ..................LCD turns on.
(2) Display data = 0 ..................LCD turns off.
•
•
•
•
•
•
•
•
•
•
•
1/64 duty cycle
Word length of display data can be switched between eight bits and six bits according to the character font.
LCD driver outputs
Interface with 80-series MPU
On-chip oscillator with one external resistor
Low power consumption
On-chip resistors to divide bias voltage, on-chip operational amplifier for LCD supply, on-chip DC-DC converter,
on-chip contrast control circuit
CMOS process
Operating voltage
Package
: 4.5 to 5.5 V
: TCP (tape carrier package)
Operating voltage for LCD drive signal : V
DD
−
V
EE
= 16.0 V (max)
: 120 column driver outputs and 64 row driver outputs
: 120 × 64 = 7.5 kbits
1
2002-03-06
T6A04A
Block Diagram
COM1
COM32
COM33
COM64
SEG1
SEG120
LCD DRIVE CIRCUIT
(32)
32-bit SHIFT REGISTER
MPX
LCD DRIVE CIRCUIT
(32)
32-bit SHIFT REGISTER
DECODER
LCD DRIVE CIRCUIT (120)
LATCH
120
DISPLAY RAM
120
×
64
=
7.5 kbits
INPUT/OUTPUT GATE
M/S
FS1
FS2
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
R
1
R
2
3
TIMING
GENERATION
CIRCUIT
OP-AMP (×5)
3
MPX
5
2
X-COUNTER
Y-ADDRESS
COUNTER/DECODER
Z-COUNTER
8
RESISTOR
LADDERS
OSCILLATOR
OP-AMP
CONTROL
REGISTER
DISPLAY
ON/OFF
REGISTER
BIT
TRANSFER
CIRCUIT
CONTRAST
CONTROL
REGISTER
X½Y COUNTER
SELECT
REGISTER
COUNTER
UP/DOWN
REGISTER
Z-ADDRESS
REGISTER
V
EE
CONTRAST
CONTROL
CIRCUIT
WORD
LENGTH
CONVERTER
REGISTER
4
8
4
INPUT
REGISTER
8
OUTPUT
REGISTER
8
V
IN
V
OUT
DC-DC
CONVERTER
C
1
C
2
INPUT/OUTPUT
BUFFER
OUTPUT BUFFER INPUT/OUTPUT
BUFFER
PM
C
L
FRM
I/F CONTROL
CIRCUIT
/CE
INPUT/OUTPUT BUFFER
COMD SCLK OSC1 OSC2 /φ
M /STB EXP /RST D/I /WR
DB0 to DB7
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2002-03-06
T6A04A
Pin Assignment
COM32
COM1
SEG1
T6A04A
(top view)
SEG120
COM33
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
/RST
/CE
/WR
D/I
EXP
M/S
OSC2
OSC1
FS2
FS1
V
DD
/φ
PM
φB
φA
Pφ
FRM
M
C
L
COMB
V
SS
/STB
V
OUT
C
2
C
1
V
IN
R
2
R
1
V
EE
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
COM64
Note 1: The above diagram shows the pin configuration of the LSI chip; it does not show the configuration of the
tape carrier package.
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2002-03-06
T6A04A
Pin Functions
Pin Name
SEG1 to SEG120
I/O
Output
Column driver output
Row driver output
●
COM1 to COM64
Output
●
●
Disable expansion mode (EXP
=
L, M/S
=
H)
→
COM1 to COM64 are enabled.
Enable expansion mode/master mode (EXP
=
H, M/S
=
H)
→
COM1 to COM32 are enabled and COM33 to COM64 are disabled.
Enable expansion mode/slave mode (EXP
=
H, M/S
=
L)
→
COM1 to COM32 are disabled and COM33 to COM64 are enabled.
Functions
Input/output for shift clock pulse
CL
I/O
●
●
Master mode (M/S
=
H)
→
Output
Slave mode (M/S
=
L)
→
Input
Input/output for frame signal
M
I/O
●
●
Master mode (M/S
=
H)
→
Output
Slave mode (M/S
=
L)
→
Input
Input/output for display synchronous signal
FRM
I/O
●
●
Master mode (M/S
=
H)
→
Output
Slave mode (M/S
=
L)
→
Input
Input/output system clock signal
Pφ,
φA, φB
I/O
●
●
Master mode (M/S
=
H)
→
Output
Slave mode (M/S
=
L)
→
Input
Input/output row signal data
COMD
I/O
●
●
DB0 to DB7
I/O
Master mode (M/S
=
H)
→
Output
Slave mode (M/S
=
L)
→
Input
Data bus
Input for data/instruction select signal
D/I
Input
●
●
D/I
=
H
→
indicates that the data on DB0 to DB7 is display data.
D/I
=
L
→
indicates that the data on DB0 to DB7 is control data.
Input for write select signal
/WR
Input
●
●
/WR
=
H
→
Read selected
/WR
=
L
→
Write selected
Input for chip enable signal
/CE
Input
●
●
/RST
Input
/WR
=
L
→
Data on DB0 to DB7 is latched on the rising edge of /CE.
/WR
=
H
→
Data appears at DB0 to DB7 while /CE is Low.
Input for reset signal
●
/RST
=
L
→
Reset state
Input for standby signal
/STB
Input
●
●
FS1, FS2
Input
Usually connected to V
DD
/STB
=
L
→
T6A04A is in standby state and cannot accept any commands or data.
Column driver signal and row driver signal are at the V
DD
level
Input for frequency selection
Input for expansion mode selection
EXP
Input
●
●
M/S
=
H
→
enables expansion mode. Two chips can be used together.
M/S
=
L
→
disables expansion mode.
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2002-03-06
T6A04A
Pin Name
I/O
Input for master/slave selection
M/S
Input
●
●
OSC1, OSC2
M/S
=
H
→
T6A04A is master chip.
M/S
=
L
→
T6A04A is slave chip.
Functions
When using the internal clock oscillator, connect a resistor between OSC1 and OSC2.
When using an external clock, connect the clock as input to OSC1 and leave OSC2 open.
Input for LCD drive bias selection
●
LCD drive bias selection is shown in the following
table
R
2
0
0
1
1
R
1
0
1
0
1
Bias
1/6
1/7
1/8
1/9
R1, R2
C1, C2
VIN
VOUT
VEE
Connected by a capacitor for DC-DC converter
Input for DC-DC converter. Connect to V
DD
.
DC-DC converter output
Power supply for LCD driver circuit
●
When using on-chip DC-DC converter, connect VEE to VOUT
M/S
=
H
→
bias voltage output
M/S
=
L
→
bias voltage input
Power supply for LCD driver circuit
VLC1 to VLC5
●
●
V
DD
VSS
PM
/φ
Power supply for logic circuit
Ground: Reference
Pre-frame signal for Toshiba T9841B
Output system clock for Toshiba T9841B
5
2002-03-06
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