DS1554
256K NV Y2KC Timekeeping RAM
www.dalsemi.com
FEATURES
Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
Clock registers are accessed identically to the
static RAM; these registers are resident in the
16 top RAM locations
Century byte register; i.e., Y2K complaint
Totally nonvolatile with over 10 years of
operation in the absence of power
Precision power-on reset
Programmable watchdog timer and RTC
alarm
BCD coded year, month, date, day, hours,
minutes, and seconds with automatic leap
year compensation valid up to the year 2100
Battery voltage level indicator flag
Power-fail write protection allows for
±10%
V
CC
power supply tolerance
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
RST
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
NC
IRQ/FT
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32-Pin Encapsulated Package
IRQ/FT
NC
NC
RST
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
X1
GND V
BAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34-Pin PowerCap
®
Module Board
(Uses DS9034PCX PowerCap)
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022101
DS1554
ORDERING INFORMATION
DS1554
DS1554P
DS1554W
DS1554WP
5V; 32-pin DIP Module
5V; 34-pin PowerCap Module board*
3.3V; 32-pin DIP Module
3.3V; 34-pin PowerCap Module board*
*DS9034PCX (PowerCap) Required:
must be ordered separately
PIN DESCRIPTION
A0-A14
DQ0-DQ7
IRQ
\FT
RST
CE
OE
WE
V
CC
GND
NC
X1, X2
V
BAT
- Address Input
- Data Input/Outputs
- Interrupt, Frequency Test Output
(Open Drain)
- Power-On Reset Output
(Open Drain)
- Chip Enable
- Output Enable
- Write Enable
- Power Supply Input
- Ground
- No Connection
- Crystal Connection
- Battery Connection
DESCRIPTION
The DS1554 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) with a RTC
alarm, watchdog timer, power-on reset, battery monitor, and 32k x 8 non-volatile static RAM. User
access to all registers within the DS1554 is accomplished with a bytewide interface as shown in Figure 1.
The RTC Registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour
BCD format. Corrections for day of month and leap year are made automatically.
The RTC Registers are double-buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers are
continuously updated; this occurs regardless of external registers settings to guarantee that accurate RTC
information is always maintained.
The DS1554 has interrupt (
IRQ
/FT) and reset (
RST
) outputs which can be used to control CPU activity.
The
IRQ
/FT interrupt output can be used to generate an external interrupt when the RTC Register values
match user programmed alarm values. The interrupt is always available while the device is powered from
the system supply and can be programmed to occur when in the battery backed state to serve as a system
wake-up. Either the
IRQ
/FT or
RST
outputs can also be used as a CPU watchdog timer, CPU activity is
monitored and an interrupt or reset output will be activated if the correct activity is not detected within
programmed limits. The DS1554 power-on reset can be used to detect a system power down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the
RST
output is used
for this function.
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DS1554
The DS1554 also contains its own power-fail circuitry, which automatically deselects the device when the
V
CC
supply enters an out of tolerance condition. This feature provides a high degree of data security
during unpredictable system operation brought on by low V
CC
levels.
PACKAGES
The DS1554 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1554P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
DS1554 BLOCK DIAGRAM Figure 1
DS1554 OPERATING MODES
Table 1
V
CC
V
CC
> V
PF
V
SO
< V
CC
<V
PF
V
CC
<V
SO
< V
PF
CE
OE
WE
V
IH
V
IL
V
IL
V
IL
X
X
X
X
V
IL
V
IH
X
X
X
V
IL
V
IH
V
IH
X
X
DQ0-DQ7
HIGH-Z
D
IN
D
OUT
HIGH-Z
HIGH-Z
HIGH-Z
MODE
DESELECT
WRITE
READ
READ
DESELECT
DATA
RETENTION
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
BATTERY
CURRENT
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DS1554
DATA READ MODE
The DS1554 is in the read mode whenever
CE
(chip enable) is low and
WE
(write enable) is high. The
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within t
AA
after the last address input is stable, providing that
CE
and
OE
access times are
satisfied. If
CE
or
OE
access times are not met, valid data will be available at the latter of chip enable
access (t
CEA
) or at output enable access time (t
OEA
). The state of the data input/output pins (DQ) is
controlled by
CE
and
OE
. If the outputs are activated before t
AA
, the data lines are driven to an
intermediate state until t
AA
. If the address inputs are changed while
CE
and
OE
remain valid, output data
will remain valid for output data hold time (t
OH
) but will then go indeterminate until the next address
access.
DATA WRITE MODE
The DS1554 is in the write mode whenever
WE
and
CE
are in their active state. The start of a write is
referenced to the latter occurring transition of
WE
or
CE
. The addresses must be held valid throughout
the cycle.
CE
and
WE
must return inactive for a minimum of t
WR
prior to the initiation of a subsequent
read or write cycle. Data in must be valid t
DS
prior to the end of the write and remain valid for t
DH
afterward. In a typical application, the
OE
signal will be high during a write cycle. However,
OE
can be
active provided that care is taken with the data bus to avoid bus contention. If
OE
is low prior to
WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on
WE
will then disable the outputs t
WEZ
after
WE
goes active.
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written and read only when V
CC
is greater than V
PF
.
However, when V
CC
is below the power-fail point V
PF
(point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. When V
CC
falls below the battery switch
point V
SO
(battery supply level), device power is switched from the V
CC
pin to the internal backup lithium
battery. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to nominal
levels.
The 3.3 volt device is fully accessible and data can be written and read only when V
CC
is greater than V
PF
.
When V
CC
falls below V
PF
, access to the device is inhibited. If V
PF
is less than V
SO
, the device power is
switched from V
CC
to the internal backup lithium battery when V
CC
drops below V
PF
. If V
PF
is greater
than V
SO
, the device power is switched from V
CC
to the internal backup lithium battery when V
CC
drops
below V
SO
. RTC operation and SRAM data are maintained from the battery until V
CC
is returned to
nominal levels.
All control, data, and address signals must be powered down when V
CC
is powered down.
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DS1554
BATTERY LONGEVITY
The DS1554 has a lithium power source that is designed to provide energy for the clock activity, and
clock and RAM data retention when the V
CC
supply is not present. The capability of this internal power
supply is sufficient to power the DS1554 continuously for the life of the equipment in which it is
installed. For specification purposes, the life expectancy is 10 years at 25°C with the internal clock
oscillator running in the absence of V
CC
. Each DS1554 is shipped from Dallas Semiconductor with its
lithium energy source disconnected, guaranteeing full energy capacity. When V
CC
is first applied at a
level greater than V
PF
, the lithium energy source is enabled for battery backup operation. Actual life
expectancy of the DS1554 will be much longer than 10 years since no internal battery energy is
consumed when V
CC
is present.
INTERNAL BATTERY MONITOR
The DS1554 constantly monitors the battery voltage of the internal batter. The Battery Low Flag (BLF)
bit of the Flags Register (B4 of 7FFF0h) is not writeable and should always be a 0 when read. If a 1 is
ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM
are questionable.
POWER-ON RESET
A temperature compensated comparator circuit monitors the level of V
CC
. When V
CC
falls to the power
fail trip point, the
RST
signal (open drain) is pulled low. When V
CC
returns to nominal levels, the
RST
signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
CLOCK OPERATIONS
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions.
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