0.16µm Process
ADVANCE
‡
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
18Mb ZBT SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High frequency and 100 percent bus utilization
Fast cycle times
Single +3.3V ±5% or +2.5V ±5% power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer sup-
ply (V
DD
Q)
Advanced control logic for minimum control signal
interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os, and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to elimi-
nate the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or Interleaved Burst Modes
Burst feature (optional)
Pin and ball/function compatibility with 2Mb, 4Mb,
and 8Mb ZBT SRAM
®
MT55L1MY18P, MT55V1MV18P,
MT55L512Y32P, MT55V512V32P,
MT55L512Y36P, MT55V512V36P
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
, 2.5V I/O
100-Pin TQFP
1
165-Ball FBGA
2
1. JEDEC Standard MS-025 BHA (LQFP).
2. JEDEC Standard MS-216 (Var. CAB-1)
OPTIONS
TQFP
MARKING
OPTIONS
• Packages
100-pin TQFP
165-ball FBGA
• Operating Temperature Range
Commercial (+10°C
≤
T
J
≤
+110°C)
TQFP
MARKING
T
F*
• Timing (Access/Cycle/MHz)
3.3V V
DD
, 3.3V, or 2.5V I/O, and + 2.5V V
DD
, 2.5 V I/O
3ns/5ns/200 MHz
-5
3.5ns/6ns/166 MHz
-6
4.2ns/7.5ns/133 MHz
-7.5
5ns/10ns/100 MHz
-10
• Configurations
3.3V V
DD
, 3.3V, or 2.5V I/O
1 Meg x 18
MT55L1MY18P
512K x 32
MT55L512Y32P
512K x 36
MT55L512Y36P
2.5V V
DD
, 2.5V I/O
1 Meg x 18
MT55V1MV18P
512K x 32
MT55V512V32P
512K x 36
MT55V512V36P
None
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/numberguide.
Part Number Example:
MT55L512Y36PT-10
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_A.fm - Rev A; Pub 6/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
0.16µm Process
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
GENERAL DESCRIPTION
®
The Micron Zero Bus Turnaround™ (ZBT ) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process. Micron’s 18Mb ZBT
SRAMs integrate a 1 Meg x 18, 512K x 32, or 512K x 36
SRAM core with advanced synchronous peripheral cir-
cuitry and a 2-bit burst counter. These SRAMs are opti-
mized for 100 percent bus utilization, eliminating any
turnaround cycles for READ to WRITE, or WRITE to
READ, transitions. All synchronous inputs pass
through registers controlled by a positive-edge-trig-
gered single clock input (CLK). The synchronous
inputs include all addresses, all data inputs, chip
enable (CE#), two additional chip enables for easy
depth expansion (CE2, CE2#), cycle start input (ADV/
LD#), synchronous clock enable (CKE#), byte write
enables (BWa#, BWb#, BWc# and BWd#), and read/
write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK) and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin/ball (MODE) that selects between interleaved and
linear burst modes. MODE may be tied HIGH, LOW or
left unconnected if burst is unused. The data-out (Q),
enabled by OE#, is registered by the rising edge of CLK.
WRITE cycles can be from one to four bytes wide as
controlled by the write control inputs.
All READ, WRITE, and DESELECT cycles are initi-
ated by the ADV/LD# input. Subsequent burst
addresses can be internally generated as controlled by
®
the burst advance pin (ADV/LD#). Use of burst mode is
optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the pipelined ZBT SRAM uses a late LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The data associated with the address is
required two cycles later, or on the rising edge of clock
cycle three.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed write
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa# con-
trols DQa pins/balls; BWb# controls DQb pins/balls;
BWc# controls DQc pins/balls; and BWd# controls
DQd pins/balls. Cycle types can only be defined when
an address is loaded, i.e., when ADV/LD# is LOW. Par-
ity/ECC bits are only available on the x36 versions.
The device is ideally suited for systems requiring
high bandwidth and zero bus turnaround delays.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
DUAL VOLTAGE I/O
The 3.3V V
DD
device is tested for 3.3V and 2.5V I/O
function. The 2.5V V
DD
device is tested for only 2.5V
I/O function.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_A.fm - Rev A; Pub 6/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
0.16µm Process
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
FUNCTIONAL BLOCK DIAGRAM
1 MEG x 18
20
SA0, SA1, SA
MODE
CLK
CKE#
K
ADDRESS
REGISTER 0
20
18
SA1
SA1'
D1
Q1
SA0
SA0'
BURST
D0
Q0
LOGIC
20
ADV/LD#
K
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
20
20
ADV/LD#
BWa#
BWb#
R/W#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
1 Meg x 9 x 2
18
WRITE
DRIVERS
18
MEMORY
ARRAY
18
S
E
N
S
E
A
M
P
S
18
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
18
D
A
T
A
S
T
E
E
R
I
N
G
18
O
U
T
P
U
T
B
U
F
F
E
R
S
18
DQs
DQPa
DQPb
E
E
18
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE#
CE#
CE2
CE2#
READ LOGIC
Notes:
1.
Functional block diagrams illustrate simplified device operation. See truth table, pin/ball descriptions, and timing diagrams for
detailed information.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_A.fm - Rev A; Pub 6/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
0.16µm Process
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
FUNCTIONAL BLOCK DIAGRAM
512K x 32/36
19
SA0, SA1, SA
MODE
CLK
CKE#
K
ADDRESS
REGISTER 0
19
17
SA1
SA1'
D1
Q1
SA0
SA0'
BURST
D0
Q0
LOGIC
19
ADV/LD#
K
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
19
19
ADV/LD#
BWa#
BWb#
BWc#
BWd#
R/W#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
36
WRITE
DRIVERS
512K x 8 x 4
(x32)
36 512K x 9 x 4 36
(x36)
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
36
R
E
G
I
S
T
E
R
S
36
D
A
T
A
S
T
E
E
R
I
N
G
36
O
U
T
P
U
T
B
U
F
F
E
R
S
36
DQs
DQPa
DQPb
DQPc
DQPd
E
E
36
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
OE#
CE#
CE2
CE2#
READ LOGIC
Notes:
1.
Functional block diagrams illustrate simplified device operation. See truth table, pin/ball descriptions, and timing diagrams for
detailed information.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_A.fm - Rev A; Pub 6/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
0.16µm Process
ADVANCE
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
PIN LAYOUT (TOP VIEW)
100-PIN TQFP
SA
NC
NC
V
DD
Q
V
SS
NC
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
V
DD
2
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NF/DQP
1
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
V
DD
2
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NF/DQPa
1
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
DD
2
V
DD
V
DD
2
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
NC
V
SS
V
DD
Q
NC
NC
NC
x32/x36
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
Notes:
1.
NF for x32 version, DQx for x36 version.
2.
Pins 14, 16, and 66 do not have to be connected directly to V
DD
if the input voltage is
≥
V
IH
.
3.
Pins 43 and 42 are reserved for address expansion; 36Mb and 72Mb, respectively.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_A.fm - Rev A; Pub 6/02
NF/DQPc
1
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
DD
2
V
DD
V
DD2
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NF/DQPd
1
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
Electronics Design Contest
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