TSPC603RVGB/Q14L datasheet, PDF

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TSPC603RVGB/Q14L: DescriptionMicroprocessor,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size449KB，38 Pages; ManufacturerThomson-CSF Compsants Specific

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Parameter Name	Attribute value
Maker	Thomson-CSF Compsants Specific
package instruction	,
Reach Compliance Code	unknown

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TSPC603R

PowerPC 603e™ RISC MICROPROCESSOR Family

PID7t-603e Specification

DESCRIPTION

The PID7t-603e implementation of PowerPC603e (after

named 603r) is a low-power implementation of reduced

instruction set computer (RISC) microprocessors PowerPC™

family. The 603r implements 32-bit effective addresses, inte-

ger data types of 8, 16 and 32 bits, and floating-point data types

of 32 and 64 bits.

The 603r is a low-power 2.5/3.3-volt design and provides four

software controllable power-saving modes.

The 603r is a superscalar processor capable of issuing and

retiring as many as three instructions per clock. Instructions

can execute out of order for increased performance ; however,

the 603r makes completion appear sequential. The 603r inte-

grates five execution units and is able to execute five instruc-

tions in parallel.

The 603r provides independent on-chip, 16-Kbyte, four-way

set-associative, physically addressed caches for instructions

and data and on-chip instruction and data memory manage-

ment units (MMUs). The MMUs contain 64-entry, two-way set-

associative, data and instruction translation lookaside buffers

that provide support for demand-paged virtual memory

address translation and variable-sized block translation.

The 603r has a selectable 32 or 64-bit data bus and a 32-bit

address bus. The 603r interface protocol allows multiple mas-

ters to complete for system resources through a central exter-

nal arbiter. The 603r supports single-beat and burst data trans-

fers for memory accesses, and supports memory-mapped I/O.

The 603r uses an advanced, 2.5/3.3-V CMOS process techno-

logy and maintains full interface compatibility with TTL devi-

ces.

The 603r integrates in system testability and debugging fea-

tures through JTAG boundary-scan capability.

G suffix

CBGA 255

Ceramic Ball Grid Array

GS suffix

CI–CGA 255

Ceramic Ball Grid Array

with Solder Column Interposer (SCI)

MAIN FEATURES

7.4 SPECint95, 6.1 SPECfp95 @ 300 MHz (estimated)

Superscalar (3 instructions per clock peak).

Dual 16KB caches.

Selectable bus clock.

32-bit compatibility PowerPC implementation.

On chip debug support.

typical = 3.5 Watts (266 MHz), full operating conditions.

Nap, doze and sleep modes for power savings.

Branch folding.

64-bit data bus (32-bit data bus option).

4-Gbyte direct addressing range.

Pipelined single/double precision float unit.

IEEE 754 compatible FPU.

IEEE P 1149-1 test mode (JTAG/C0P).

int

max = 300 MHz.

bus

max = 75 MHz.

Compatible CMOS input / TTL Output.

SCREENING / QUALITY / PACKAGING

This product is manufactured in full compliance with:

CI–CGA 255 : MIL-STD-883 class Q or According to TCS

standards (planned)

CBGA 255 : Upscreenings based upon TCS standards

Full military temperature range (T

= -55°C, T

= +125°C)

Industrial temperature range (T

= -40°C, T

= +110°C)

Internal // I/O Power Supply = 2.5

5 % // 3.3 V

5 %.

255 pin CBGA package and 255 pin CBGA with SCI (CI–

CGA) package.

January 1999

1/38

TSPC603R

A. GENERAL DESCRIPTION

Fetch

Unit

Completion

Unit

Dispatch

Unit

Branch

Unit

Integer

Unit

Gen

Reg

Unit

Gen

Re-

name

Load/

Store

Unit

Re-

name

Reg

File

Float

Unit

D MMU

16K Data Cache

I MMU

16K Inst. Cache

Bus Interface Unit

32b

address

64b

data

System Bus

Figure 1 :

Block diagram

1. INTRODUCTION

The 603r is a low-power implementation of the PowerPC microprocessor family of reduced instruction set commuter (RISC) micro-

processors. The 603r implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer

data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC

architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.

The 603r provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in

nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management

mode that causes the functional units in the 603r to automatically enter a low-power mode when the functional units are idle without

affecting operational performance, software execution, or any external hardware.

The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute

out of order for increased performance ; however, the 603r makes completion appear sequential.

The 603 e integrates five execution units - an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store

unit (LSU) and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with

rapid execution times yield high efficiency and throughput for 603r-based systems. Most integer instructions execute in one clock

cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.

The 603r provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed caches for instructions and data

and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data

and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address

translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The

603r also supports block address translation through the use of two independent instruction and data block address translation (IBAT

and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during

block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT

translation takes priority.

The 603r has a selectable 32 - or 64-bit - data bus and a 32-bit address bus. The 603r interface protocol allows multiple masters to

compete for system resources through a central external arbiter. The 603r provides a three-state coherency protocol that supports

the exclusive, modified, and invalid cache states. This protocol as a compatible subset of the MESI (modified/exclusive/shared/in-

valid) four-state protocol and operates coherently in systems that contain four-state caches. The 603r supports single-beat and burst

data transfers for memory accesses, and supports memory-mapped I/O.

The 603r uses an advanced, 0.29

5 metal layer CMOS process technology and maintains full interface compatibility with TTL

devices.

3/38

TSPC603RVGB/Q14L Related Products

	TSPC603RVGB/Q14L	TSPC603RMGB/T8L	TSPC603RMGB/T12L	TSPC603RVGB/Q12L	TSPC603RVGSB/Q10L	TSPC603RVGSB/Q12L	TSPC603RVGSB/Q6L
Description	Microprocessor,	Microprocessor	Microprocessor	Microprocessor,	Microprocessor,	Microprocessor,	Microprocessor,
Maker	Thomson-CSF Compsants Specific	Thomson-CSF Compsants Specific	Thomson-CSF Compsants Specific	Thomson-CSF Compsants Specific	Thomson-CSF Compsants Specific	Thomson-CSF Compsants Specific	Thomson-CSF Compsants Specific
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown

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