DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA1856
P-CHANNEL MOS FIELD EFFECT TRANSISTOR
FOR SWITCHING
DESCRIPTION
The
µ
PA1856 is a switching device which can be
driven directly by a 2.5-V power source.
The
µ
PA1856 features a low on-state resistance and
excellent switching characteristics, and is suitable for
applications such as power switch of portable machine
and so on.
8
PACKAGE DRAWING (Unit : mm)
5
1
2, 3
4
5
6, 7
8
:Drain1
:Source1
:Gate1
:Gate2
:Source2
:Drain2
1.2 MAX.
1.0±0.05
0.25
3°
+5°
–3°
0.1±0.05
0.5
0.6
+0.15
–0.1
FEATURES
•
Can be driven by a 2.5-V power source
•
Low on-state resistance
R
DS(on)1
= 45 mΩ MAX. (V
GS
= –4.5 V, I
D
= –2.5 A)
R
DS(on)2
= 48 mΩ MAX. (V
GS
= –4.0 V, I
D
= –2.5 A)
R
DS(on)3
= 72 mΩ MAX. (V
GS
= –2.7 V, I
D
= –2.5 A)
R
DS(on)4
= 77 mΩ MAX. (V
GS
= –2.5 V, I
D
= –2.5 A)
1
4
0.145 ±0.055
3.15 ±0.15
3.0 ±0.1
6.4 ±0.2
4.4 ±0.1
1.0 ±0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power TSSOP8
0.65
0.27
+0.03
–0.08
0.8 MAX.
µ
PA1856GR-9JG
0.1
0.10 M
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
Drain to Source Voltage
Gate to Source Voltage
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
EQUIVALENT CIRCUIT
–20
±12
±4.5
±18
2.0
150
V
V
A
A
W
°C
°C
Gate1
Gate
Protection
Diode
Source1
Drain1
Drain2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
T
ch
T
stg
Body
Diode
Gate2
Gate
Protection
Diode
Source2
Body
Diode
Total Power Dissipation
Channel Temperature
Storage Temperature
–55 to +150
Notes 1.
PW
≤
10
µ
s, Duty Cycle
≤
1 %
2
2.
Mounted on ceramic substrate of 5000 mm x 1.1 mm
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
D13808EJ2V0DS00 (2nd edition)
Date Published March 2000 NS CP(K)
Printed in Japan
The mark
•
shows major revised points.
©
1998, 1999
µ
PA1856
ELECTRICAL CHARACTERISTICS (T
A
= 25 °C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
SYMBOL
I
DSS
I
GSS
V
GS(off)
| y
fs
|
R
DS(on)1
R
DS(on)2
R
DS(on)3
R
DS(on)4
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Diode Forward Voltage
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
TEST CONDITIONS
V
DS
= –20 V, V
GS
= 0 V
V
GS
= ±12 V, V
DS
= 0 V
V
DS
= –10 V, I
D
= –1 mA
V
DS
= –10 V, I
D
= –2.5 A
V
GS
= –4.5 V, I
D
= –2.5 A
V
GS
= –4.0 V, I
D
= –2.5 A
V
GS
= –2.7 V, I
D
= –2.5 A
V
GS
= –2.5 V, I
D
= –2.5 A
V
DS
= –10 V
V
GS
= 0 V
f = 1 MHz
V
DD
= –10 V
I
D
= –2.5 A
V
GS(on)
= –4.0 V
R
G
= 10
Ω
V
DS
= –16 V
I
D
= –4.5 A
V
GS
= –4.0 V
I
F
= 4.5 A, V
GS
= 0 V
I
F
= 4.5 A, V
GS
= 0 V
di/dt = 10 A /
µ
s
–0.5
3
–1.1
8.8
37
39
52
57
700
208
100
300
528
242
698
6.0
2.1
2.8
0.86
32
2.2
45
48
72
77
MIN.
TYP.
MAX.
–10
±10
–1.5
UNIT
µ
A
µ
A
V
S
mΩ
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
•
•
Reverse Recovery Time
Reverse Recovery Charge
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
R
L
PG.
R
G
V
DD
I
D
(−)
V
GS
(−)
0
τ
τ
= 1
µ
s
Duty Cycle
≤
1 %
I
D
Wave Form
V
GS
(−)
V
GS
Wave Form
I
G
=
−2
mA
V
GS
(on)
90 %
R
L
V
DD
0
10 %
PG.
90 %
90 %
50
Ω
I
D
0 10 %
10 %
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
2
Data Sheet D13808EJ2V0DS00
µ
PA1856
TYPICAL CHARACTERISTICS (T
A
= 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
•
−100
FORWARD BIAS SAFE OPERATING AREA
dT - Derating Factor - %
I
D
- Drain Current - A
−10
I
D
(pulse)
d
PW
ite V)
im4.5
=1
)
L
−
(on
=
PW
ms
S
R
D
V
GS
=1
I
D
(
DC
)
(@
PW
60
−1
0
ms
=1
00
ms
DC
40
20
−0.1
T
A
= 25 ˚C
Single Pulse
Mounted on Ceramic
Substrate of 5000 mm
2
x 1.1 mm
P
D
(FET1) : P
D
(FET2) = 1:1
0
30
60
90
120
T
A
- Ambient Temperature -
˚C
150
−0.01
−0.1
−10
−1
V
DS
- Drain to Source Voltage - V
−100
•
−
20
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
V
GS
=
−10
V
−4.5
V
−4.0
V
I
D
- Drain Current - A
TRANSFER CHARACTERISTICS
−100
−10
−1
−0.1
−0.01
−0.001
T
A
= 125˚C
75˚C
25˚C
−
25˚C
V
DS =
−10
V
I
D
- Drain Current - A
−
16
−
12
−2.5
V
−
8
−
4
−0.0001
−0.00001
0
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
0
0.0
−
0.2
−
0.4
−
0.6
−
0.8
−
1.0
V
DS
- Drain to Source Voltage - V
V
GS
- Gate to Sorce Voltage - V
FORWARD TRANSFER ADMITTANCE Vs.
DRAIN CURRENT
100
| y
fs
| - Forward Transfer Admittance - S
•
V
GS(off)
- Gate to Source Cut-off Voltage - V
−1.5
V
DS
=
−
10 V
I
D
=
−
1 mA
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
V
DS
=
−10V
10
T
A
=
−25
˚C
25˚C
75˚C
125˚C
−1.0
1
0.1
−0.5
−50
0
50
100
150
0.01
−0.01
−0.1
−1
I
D
- Drain Current - A
−10
−100
T
ch
- Channel Temperature - ˚C
Data Sheet D13808EJ2V0DS00
3
µ
PA1856
R
DS(on)
- Drain to Source On-State Resistance - mΩ
100
R
DS(on)
- Drain to Source On-State Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
V
GS
=
−2.5
V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
100
V
GS
=
−2.7
V
80
T
A
= 125˚C
80
T
A
= 125˚C
75˚C
60
25˚C
60
75˚C
25˚C
−
25˚C
40
−0.01
−0.1
−1
−10
−100
−
25˚C
40
−0.01
−0.1
−1
−10
−100
I
D
- Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
70
V
GS
=
−4.0
V
I
D
- Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
60
V
GS
=
−4.5
V
T
A
= 125˚C
R
DS(on)
- Drain to Source On-State Resistance - mΩ
R
DS(on)
- Drain to Source On-State Resistance - mΩ
60
T
A
= 125˚C
50
75˚C
50
T
A
= 75˚C
40
25˚C
40
T
A
= 25˚C
T
A
=
−
25˚C
30
−
25˚C
30
−0.01
−0.1
−1
−10
−100
20
−0.01
−0.1
−1
−10
−100
I
D
- Drain Current - A
I
D
- Drain Current - A
R
DS (on)
- Drain to Source On-state Resistance - mΩ
100
R
DS (on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON STATE RESISTANCE vs.
CHANNEL TEMPERATURE
I
D
=
−2.5
A
V
GS
=
−2.5
V
−2.7
V
60
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
120
I
D
=
−2.5
A
80
100
80
−4.0
V
−4.5
V
60
40
40
20
0
20
−50
T
ch
0
50
100
- Channel Temperature -˚C
150
−
2
−
4
−
6
−
8
−
10
−
12
V
GS
- Gate to Source Voltage - V
4
Data Sheet D13808EJ2V0DS00
µ
PA1856
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
10000
SWITCHING CHARACTERISTICS
10000
t
d(on)
, t
r
, t
d(off)
, t
f
- Switchig Time - ns
Ciss, Coss, Crss - Capacitance - pF
f = 1 MHz
V
GS
= 0V
1000
C
iss
1000
t
f
t
r
t
d(on)
t
d(off)
100
V
DD
=
−10
V
V
GS(on)
=
−4.0
V
R
G
= 10
Ω
−1
I
D
- Drain Current - A
−10
100
C
oss
C
rss
10
−0.1
−1
−10
−100
10
−0.1
V
DS
- Drain to Source Voltage - V
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
DYNAMIC INPUT CHARACTERISTICS
−8
I
F
- Source to Drain Current - A
V
GS
- Gate to Source Voltage - V
100
I
D
=
−4.5
A
V
DD
=
−16
V
−10
V
10
−6
1
−4
0.1
−2
0.01
0.4
0
0.6
0.8
1.0
1.2
0
1
2
V
F(S-D)
- Source to Drain Voltage - V
3 4
5 6
7
Q
G
- Gate Charge - nC
8
9
10
•
1000
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
r
th(t)
- Transient Thermal Resistance - ˚C/W
100
62.5˚C/W
10
1
Mounted on ceramic substrate
of 5000 mm
2
x 1.1 mm
Single Pulse
P
D
(FET1) : P
D
(FET2) = 1:1
0.1
1m
10m
100m
1
10
100
1000
PW - Pulse Width - S
Data Sheet D13808EJ2V0DS00
5
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