DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA1850
P-CHANNEL MOS FIELD EFFECT TRANSISTOR
FOR SWITCHING
DESCRIPTION
The
µ
PA1850 is a switching device which can be
driven directly by a 2.5
-
V power source.
The
µ
PA1850 features a low on-state resistance and
excellent switching characteristics, and is suitable for
applications such as power switch of portable machine
and so on.
8
PACKAGE DRAWING (Unit : mm)
5
1
2, 3
4
5
6, 7
8
:Drain1
:Source1
:Gate1
:Gate2
:Source2
:Drain2
1.2 MAX.
1.0±0.05
0.25
3°
+5°
–3°
0.1±0.05
0.5
0.6
+0.15
–0.1
FEATURES
•
Can be driven by a 2.5-V power source
•
Low on-state resistance
R
DS(on)1
= 115 mΩ MAX. (V
GS
= –4.5 V, I
D
= –1.5 A)
R
DS(on)2
= 130 mΩ MAX. (V
GS
= –4.0 V, I
D
= –1.5 A)
R
DS(on)3
= 200 mΩ MAX. (V
GS
= –2.5 V, I
D
= –1.5 A)
•
Built-in G-S protection diode against ESD
1
4
0.145 ±0.055
3.15 ±0.15
3.0 ±0.1
6.4 ±0.2
4.4 ±0.1
1.0 ±0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power TSSOP8
0.65
0.27
+0.03
–0.08
0.8 MAX.
µ
PA1850GR-9JG
0.1
0.10 M
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
Drain to Source Voltage
Gate to Source Voltage
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
T
ch
T
stg
–12
–10/+5
V
V
A
A
W
°C
°C
Gate
Protection
Diode
Gate1
EQUIVALENT CIRCUIT
Drain1
Drain2
#
2.5
#
1
0
2.0
150
–55 to +150
Total Power Dissipation
Channel Temperature
Storage Temperature
Body
Diode
Gate2
Body
Diode
Notes 1.
PW
≤
10
µ
s, Duty Cycle
≤
1 %
2
2.
Mounted on ceramic substrate of 5000 mm x 1.1 mm
Remark
Source1
Gate
Protection
Diode
Source2
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
D11818EJ2V0DS00 (2nd edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark
5
shows major revised points.
©
1997, 2000
µ
PA1850
ELECTRICAL CHARACTERISTICS (T
A
= 25 °C)
CHARACTERISTICS
Drain Cut-off Current
Gate Leakage Current
SYMBOL
I
DSS
I
GSS
V
GS(off)
| y
fs
|
R
DS(on)1
R
DS(on)2
R
DS(on)3
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Diode Forward Voltage
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
TEST CONDITIONS
V
DS
= –12 V, V
GS
= 0 V
V
GS
=
#
10 V, V
DS
= 0 V
V
DS
= –10 V, I
D
= –1 mA
V
DS
= –10 V, I
D
= –1.5 A
V
GS
= –4.5 V, I
D
= –1.5 A
V
GS
= –4.0 V, I
D
= –1.5 A
V
GS
= –2.5 V, I
D
= –1.5 A
V
DS
= –10 V
V
GS
= 0 V
f = 1 MHz
V
DD
= –10 V
I
D
= –1.5 A
V
GS(on)
= –4.0 V
R
G
= 10
Ω
V
DD
= –10 V
I
D
= –2.5 A
V
GS
= –4.0 V
I
F
= 2.5 A, V
GS
= 0 V
I
F
= 2.5 A, V
GS
= 0 V
di/dt = 10 A /
µ
s
–0.5
2.0
–1.0
5.0
80
85
127
260
300
45
120
420
520
430
12
2
5
0.80
750
950
115
130
200
MIN.
TYP.
MAX.
–10
#
10
UNIT
µ
A
µ
A
V
S
mΩ
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
5
5
Gate to Source Cut-off Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
–1.5
5
5
Reverse Recovery Time
Reverse Recovery Charge
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
R
L
PG.
R
G
V
DD
I
D
(−)
V
GS
(−)
0
τ
τ
= 1
µ
s
Duty Cycle
≤
1 %
I
D
Wave Form
V
GS
(−)
V
GS
Wave Form
I
G
=
−2
mA
V
GS
(on)
90 %
R
L
V
DD
0
10 %
PG.
90 %
90 %
50
Ω
I
D
0 10 %
10 %
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
2
Data Sheet D11818EJ2V0DS00
µ
PA1850
5
TYPICAL CHARACTERISTICS (T
A
= 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
FORWARD BIAS SAFE OPERATING AREA
−100
P
dT - Derating Factor - %
60
I
D
- Drain Current - A
−10
W
d
I
D
(pulse)
=1
ite V)
Lim 4.0
ms
)
on
−
10
S(
=
ms
R
D
V
GS
I
D
(
DC
)
(@
10
0m
s
DC
−1
40
20
0
Single Pulse
Mounted on Ceramic
2
Substrate of 5000 mm x 1.1mm
−0.01
P
D
(FET1) : P
D
(FET2) = 1:1
−0.1
30
60
90
120
T
A
- Ambient Temperature -
˚C
150
−0.1
−1.0
−10.0
−100.0
V
DS
- Drain to Source Voltage - V
V
GS(off)
- Gate to Source Cut-off Voltage - V
TRANSFER CHARACTERISTICS
−10
V
DS
=
−10
V
−1.5
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
V
DS
=
−10
V
I
D
=
−1
mA
I
D
- Drain Current - A
−1
−1
−0.1
T
A
= 125 ˚C
75 ˚C
25 ˚C
−25
˚C
−0.5
−0.01
−0.001
0
−1
−2
−3
0
−50
0
50
100
150
V
GS
- Gate to Source Voltage - V
T
ch
- Channel Temperature - ˚C
100
| y
fs
| - Forward Transfer Admittance - S
R
DS(on)
- Drain to Source On-state Resistance - mΩ
FORWARD TRANSFER ADMMITTANCE vs.
DRAIN CURRENT
V
DS
=
−10
V
T
A
=
−25
˚C
25
˚C
75
˚C
125
˚C
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
250
V
GS
=
−
2.5 V
10
200
T
A
= 125˚C
150
75˚C
25˚C
1
100
−25˚C
0.1
−0.1
−1
−10
−100
I
D
- Drain Current - A
50
−0.1
−1
−10
−100
I
D
- Drain Current - A
Data Sheet D11818EJ2V0DS00
3
µ
PA1850
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
200
V
GS
=
−
4.0 V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
120
V
GS
=
−
10 V
R
DS(on)
- Drain to Source On-state Resistance - mΩ
R
DS(on)
- Drain to Source On-state Resistance - mΩ
100
150
T
A
= 125˚C
80
T
A
= 125
˚C
75
˚C
100
75˚C
25˚C
−25˚C
60
25
˚C
−25
˚C
50
40
0
−0.1
−1
−10
−100
20
−0.1
−1
−10
−100
I
D
- Drain Current - A
I
D
- Drain Current - A
R
DS (on)
- Drain to Source On-state Resistance - mΩ
200
R
DS (on)
- Drain to Source On-state Resistance - mΩ
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
I
D
=
−1.5
A
V
GS
=
−2.5
V
160
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
500
I
D
=
−1.5
A
400
120
−4.0
V
−10
V
300
80
200
40
100
0
−50
T
ch
0
0
0
50
100
- Channel Temperature -˚C
150
−
2
−
4
−
6
−
8
−
10
V
GS
- Gate to Source Voltage - V
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
td
(on)
, tr, td
(off)
, tf - Swwitchig Time - ns
Ciss, Coss, Crss - Capacitance - pF
1000
f = 1 MHz
C
oss
C
iss
1000
tf
tr
td
(off)
100
C
rss
100
td
(on)
10
−1
−10
V
DS
- Drain to Source Voltage - V
−100
10
−0.1
V
DD
=
−10
V
V
GS
(
on
) =
−4.0
V
R
G
= 10
Ω
−1
−10
I
D
- Drain Current - A
4
Data Sheet D11818EJ2V0DS00
µ
PA1850
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
10
−5
DYNAMIC INPUT CHARACTERISTICS
I
F
- Source to Drain Current - A
V
GS
- Gate to Source Voltage - V
I
D
=
-2.5
A
V
DD
=
-4
V
V
DD
=
-10
V
−4
−3
−2
−1
1
0.1
0.4
V
GS
= 0 V
0.8
1.2
1.6
0
0
3
V
F(S-D)
- Source to Drain Voltage - V
6
9
12
Q
G
- Gate Charge - nC
15
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
r
th(t)
- Transient Thermal Resistance - ˚C/W
100
62.5˚C/W
10
1
Mounted on Ceramic Substrate
of 5000 mm
2
x 1.1 mm
Single Pulse
P
D
(FET1) : P
D
(FET2) = 1:1
0.1
1m
10m
100m
1
10
PW - Pulse Width - S
100
1000
Data Sheet D11818EJ2V0DS00
5
ADI Reference Circuit
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