K4X56323PG-7GC30 datasheet, PDF

Datasheet> All Categories > storage> storage> K4X56323PG-7GC30

K4X56323PG-7GC30: DescriptionDDR DRAM, 8MX32, 6ns, CMOS, PBGA90, FBGA-90; Categorystorage storage; File Size243KB，23 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

Download Datasheet Parametric Compare View All

K4X56323PG-7GC30 Overview

DDR DRAM, 8MX32, 6ns, CMOS, PBGA90, FBGA-90

K4X56323PG-7GC30 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	VFBGA, BGA90,9X15,32
Contacts	90
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	2,4,8,16
JESD-30 code	R-PBGA-B90
length	13 mm
memory density	268435456 bit
Memory IC Type	DDR DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	90
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	8MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA90,9X15,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1 mm
self refresh	YES
Continuous burst length	2,4,8,16
Maximum standby current	0.0003 A
Maximum slew rate	0.14 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8 mm

K4X56323PG-7GC30 Preview

K4X56323PG - 7(8)E/G

8M x32 Mobile-DDR SDRAM

FEATURES

Mobile-DDR SDRAM

• 1.8V power supply, 1.8V I/O power

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

•

MRS cycle with address key programs

- CAS Latency ( 2, 3 )

Burst Length ( 2, 4, 8, 16 )

- Burst Type (Sequential & Interleave)

- Partial Self Refresh Type ( Full, 1/2, 1/4 Array )

- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )

• Internal Temperature Compensated Self Refresh

• Deep Power Down Mode

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).

• Data I/O transactions on both edges of data strobe, DM for masking.

• Edge aligned data output, center aligned data input.

• No DLL; CK to DQS is not synchronized.

• DM0 - DM3 for write masking only.

•

Auto refresh duty cycle

15.6us for -25 to 85

°C

Operating Frequency

DDR266

Speed @CL2

Speed @CL3

Note :

1. CAS Latency

DDR222

66Mhz

111Mhz

83Mhz

133Mhz

Address configuration

Organization

8M x32

- DM is internally loaded to match DQ and DQS identically.

Bank

BA0,BA1

Row

A0 - A11

Column

A0 - A8

Ordering Information

Part No.

K4X56323PG-7(8)E/GC3

K4X56323PG-7(8)E/GCA

Max Freq.

133MHz(CL=3),83MHz(CL=2)

111MHz(CL=3),66MHz(CL=2)

Interface

LVCMOS

Package

90FBGA

Pb (Pb Free)

- 7(8)E 90FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25

°C

~ 85

°C)

- 7(8)G : 90 FBGA Pb(Pb Free), Low Power, Extended Temperature(-25

°C

~ 85

°C)

- C3/CA : 133MHz(CL=3)/111MHz(CL=3)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PRO-

VIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could

result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or pro-

visions may apply.

January 2006

K4X56323PG - 7(8)E/G

FUNCTIONAL BLOCK DIAGRAM

Mobile-DDR SDRAM

LWE

I/O Control

CK, CK

Data Input Register

Serial to parallel

LDM

Bank Select

1Mx64

Output Buffer

2-bit prefetch

Sense AMP

Refresh Counter

Row Buffer

Row Decoder

1Mx64

X32

DQi

Address Register

CK, CK

ADD

Column Decoder

LCBR

LRAS

Col. Buffer

Latency & Burst Length

Strobe

Gen.

Data Strobe

Programming Register

LCKE

LRAS LCBR

LWE

LCAS

LWCBR

LDM

Timing Register

DM Input Register

CK, CK

CKE

RAS

CAS

January 2006

K4X56323PG - 7(8)E/G

< Bottom View

Ball Name

CK, CK

CKE

A0 ~ A11

BA0 ~ BA1

RAS

DDQ

SSQ

DDQ

SSQ

CKE

SSQ

DDQ

SSQ

DDQ

Mobile-DDR SDRAM

< Top View

90Ball(6x15) FBGA

SSQ

DQ30

DQ28

DQ26

DQ24

DQ8

DQ10

DQ12

DQ14

SSQ

DDQ

DQ17

DQ19

DQ21

DQ23

A10/AP

DQ7

DQ5

DQ3

DQ1

DDQ

DQ16

DQ18

DQ20

DQ22

DQS2

DM2

CAS

BA0

DM0

DQS0

DQ6

DQ4

DQ2

DQ0

SSQ

DDQ

SSQ

DDQ

RAS

BA1

DDQ

SSQ

DDQ

SSQ

Package Dimension and Pin Configuration

DQ31

DQ29

DQ27

DQ25

DQS3

DM3

A11

DM1

DQS1

DQ9

DQ11

DQ13

DQ15

Ball Function

System Differential Clock

Chip Select

Clock Enable

Address

Bank Select Address

Row Address Strobe

Column Address Strobe

Write Enable

Data Input Mask

Data Strobe

Data Input/Output

Power Supply/Ground

Data Output Power/Ground

[Unit::mm]

< Top

View

CAS

DM0~3

DQS0~3

DQ0 ~ 31

DDQ

SSQ

#A1 Ball Origin Indicator

SAMSUNG

Week

K4X56323PG-XXXX

Symbol

Min

0.25

7.90

12.90

0.45

Typ

8.00

6.40

13.00

11.20

0.80

0.50

Max

1.00

8.10

13.10

0.55

0.10

January 2006

K4X56323PG - 7(8)E/G

Input/Output Function Description

SYMBOL

CK, CK

TYPE

Input

DESCRIPTION

Mobile-DDR SDRAM

Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the

crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from

CK/CK.

Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input

buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF

REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any banks). CKE is

synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input

buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are

contrived for low standby power consumption.

Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder.

All commands are masked when CS is registered HIGH. CS provides for external bank selection on

systems with multiple banks. CS is considered part of the command code.

Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled

HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM

pins include dummy loading internally, to match the DQ and DQS loading. For the x32, DM0

corresponds to the data on DQ0-DQ7 ; DM1 corresponds to the data on DQ8-DQ15, DM2 corresponds

to the data on DQ16-DQ23, DM3 corresponds to the data on DQ24-DQ31

Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE

command is being applied.

Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO

PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the

respective bank. A10 sampled during a PRECHARGE command

determines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only

one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the

op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode register

( mode register or extended mode register ) is loaded during the MODE REGISTER SET command.

Data Input/Output : Data bus

Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write

data. it is used to fetch write data. For the x32, DQS0 corresponds to the data on DQ0-DQ7 ; DQS1

corresponds to the data on DQ8-DQ15,DQS2 corresponds to the data on DQ16-DQ23, DQS3 corre-

sponds to the data on DQ24-DQ31

No Connect : No internal electrical connection is present.

DQ Power Supply : 1.7V to 1.95V

DQ Ground.

Power Supply : 1.7V to 1.95V

Ground.

CKE

Input

RAS, CAS, WE

DM0,DM1,

DM2,DM3

Input

BA0, BA1

A [n : 0]

Input

DQS0,DQS1,

DQS2,DQS3

I/O

VDDQ

VSSQ

VDD

VSS

Supply

January 2006

K4X56323PG - 7(8)E/G

Functional Description

Mobile-DDR SDRAM

POWER

APPLIED

POWER

CKEH

DEEP

POWER

DOWN

PRECHARGE

ALL BANKS

DEEP

POWER

DOWN

PARTIAL

SELF

REFRESH SELF

REFRESH

REFS

REFSX

MRS

EMRS

MRS

IDLE

ALL BANKS

PRECHARGED

REFA

AUTO

REFRESH

CKEL

CKEH

ACT

POWER

DOWN

POWER

DOWN

CKEH

ROW

ACTIVE

BURST STOP

READ

WRITEA

READA

READ

CKEL

WRITE

WRITEA

WRITE

WRITEA

READA

PRE

READA

WRITEA

READA

PRE

PRECHARGE

PREALL

Automatic Sequence

Command Sequence

Figure.1 State diagram

January 2006

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

K4X56323PG-7GC30 Related Products

	K4X56323PG-7GC30	K4X56323PG-8GC30	K4X56323PG-8EC30	K4X56323PG-7EC30	K4X56323PG-8ECA0	K4X56323PG-8GCA0	K4X56323PG-7ECA0	K4X56323PG-7GCA0
Description	DDR DRAM, 8MX32, 6ns, CMOS, PBGA90, FBGA-90	DDR DRAM, 8MX32, 6ns, CMOS, PBGA90, LEAD FREE, FBGA-90	DDR DRAM, 8MX32, 6ns, CMOS, PBGA90, LEAD FREE, FBGA-90	DDR DRAM, 8MX32, 6ns, CMOS, PBGA90, FBGA-90	DDR DRAM, 8MX32, 6ns, CMOS, PBGA90, LEAD FREE, FBGA-90	DDR DRAM, 8MX32, 6ns, CMOS, PBGA90, LEAD FREE, FBGA-90	DDR DRAM, 8MX32, 6ns, CMOS, PBGA90, FBGA-90	DDR DRAM, 8MX32, 6ns, CMOS, PBGA90, FBGA-90
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32	VFBGA, BGA90,9X15,32
Contacts	90	90	90	90	90	90	90	90
Reach Compliance Code	compliant	unknown	compliant	compliant	compliant	compliant	compli	compli
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	6 ns	6 ns	6 ns	6 ns	6 ns	6 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz	133 MHz	133 MHz	133 MHz	111 MHz	111 MHz	111 MHz	111 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
interleaved burst length	2,4,8,16	2,4,8,16	2,4,8,16	2,4,8,16	2,4,8,16	2,4,8,16	2,4,8,16	2,4,8,16
JESD-30 code	R-PBGA-B90	R-PBGA-B90	R-PBGA-B90	R-PBGA-B90	R-PBGA-B90	R-PBGA-B90	R-PBGA-B90	R-PBGA-B90
length	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm
memory density	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bi	268435456 bi
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	32	32	32	32	32	32	32	32
Number of functions	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1
Number of terminals	90	90	90	90	90	90	90	90
word count	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words
character code	8000000	8000000	8000000	8000000	8000000	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-25 °C	-25 °C	-25 °C	-25 °C	-25 °C	-25 °C	-25 °C	-25 °C
organize	8MX32	8MX32	8MX32	8MX32	8MX32	8MX32	8MX32	8MX32
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VFBGA	VFBGA	VFBGA	VFBGA	VFBGA	VFBGA	VFBGA	VFBGA
Encapsulate equivalent code	BGA90,9X15,32	BGA90,9X15,32	BGA90,9X15,32	BGA90,9X15,32	BGA90,9X15,32	BGA90,9X15,32	BGA90,9X15,32	BGA90,9X15,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192	8192	8192
Maximum seat height	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
self refresh	YES	YES	YES	YES	YES	YES	YES	YES
Continuous burst length	2,4,8,16	2,4,8,16	2,4,8,16	2,4,8,16	2,4,8,16	2,4,8,16	2,4,8,16	2,4,8,16
Maximum standby current	0.0003 A	0.0003 A	0.0003 A	0.0003 A	0.0003 A	0.0003 A	0.0003 A	0.0003 A
Maximum slew rate	0.14 mA	0.14 mA	0.14 mA	0.14 mA	0.125 mA	0.125 mA	0.125 mA	0.125 mA
Maximum supply voltage (Vsup)	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm

Recommended Resources

Power MOSFET inverter

COMPAQ 1504 type TTL color display power supply circuit diagram

160m band preamplifier with ferrite loop antenna

20HZ-20KHZ variable audio oscillator circuit diagram

LA3210 power amplifier circuit

Russian standard caller ID box circuit

I want to implement the TCP/IP protocol stack on a microcontroller. Which series of microcontrollers is more suitable?: I want to implement TCP/IP protocol stack on a microcontroller. Which microcontroller is more suitable? My tutor said that PIC is better. Can you give me some advice? Is it more convenient to use 16-b...; dfsfds MCU

I want to output an analog signal through DA. How can I set the filter to make it smooth?: The original signal is a sine wave-like signal with a period of 10 microseconds, a signal frequency of 90-110KHz, and a center frequency of 100KHz. During sampling, a point is obtained every 1.25 micr...; xiaoqiao2395 ARM Technology

filter: What is the cutoff frequency of the filter? What is the center frequency?...; daisylee Analog electronics

Follow TE to win a Samsung phone and watch the video to learn more about TE - the global expert in connectivity solutions: [font=微软雅黑][size=3]:pleased:Benefits are here. Follow TE for a chance to win Samsung phones, AMP crimping pliers, wireless routers and other heavyweight prizes[/size][/font] [font=微软雅黑][size=3] [/size...; eric_wang Talking

ARM-LINUX study notes (Part 2): [i=s] This post was last edited by Weimo Fanchen on 2015-5-19 22:43 [/i] [align=center]Makefile[/align] In the process of learning embedded Linux, we often use the make command, and generally the foll...; 微末凡尘 ARM Technology

Free evaluation - Topmicro intelligent display module (6) PIP small keyboard: [i=s]This post was last edited by wenyangzeng on 2021-11-5 13:20[/i]Free evaluation - Topmicro intelligent display module (6) PIP small keyboardCreate a new projectSet page colorAdd a string controlAd...; wenyangzeng Test/Measurement

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components