UPD4481362GF-C50 datasheet, PDF

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UPD4481362GF-C50: Description256KX36 ZBT SRAM, 3.2ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100; Categorystorage storage; File Size224KB，40 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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UPD4481362GF-C50 Overview

256KX36 ZBT SRAM, 3.2ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100

UPD4481362GF-C50 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.2 ns
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	9437184 bit
Memory IC Type	ZBT SRAM
memory width	36
Number of functions	1
Number of terminals	100
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD4481162, 4481182, 4481322, 4481362

8M-BIT ZEROSB

SRAM

PIPELINED OPERATION

Description

The

PD4481162 is a 524,288-word by 16-bit, the

PD4481182 is a 524,288-word by 18-bit, the

PD4481322 is a

262,144-word by 32-bit and the

PD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with

advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD4481162,

PD4481182,

PD4481322 and

PD4481362 are optimized to eliminate dead cycles for read to

write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit

burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the

single clock input (CLK).

The

PD4481162,

PD4481182,

PD4481322 and

PD4481362 are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).

In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal

operation.

The

PD4481162,

PD4481182,

PD4481322 and

PD4481362 are packaged in 100-pin PLASTIC LQFP with a 1.4

mm package thickness or 165-pin TAPE FBGA for high density and low capacitive loading.

Features

•

Low voltage core supply (A version : V

= 3.3 ± 0.165V, C version : V

= 2.5 ± 0.125V)

•

Synchronous operation

•

100 percent bus utilization

•

Internally self-timed write control

•

Burst read / write : Interleaved burst and linear burst sequence

•

Fully registered inputs and outputs for pipelined operation

•

All registers triggered off positive clock edge

•

3.3V or 2.5V LVTTL Compatible : All inputs and outputs

•

Fast clock access time : 3.2 ns (200 MHz), 3.5 ns (167 MHz) , 4.2 ns (133 MHz)

•

Asynchronous output enable : /G

•

Burst sequence selectable : MODE

•

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

•

Separate byte write enable : /BW1 - /BW4 (

PD4481322 and

PD4481362), /BW1 - /BW2 (

PD4481162 and

PD4481182)

•

Three chip enables for easy depth expansion

•

Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15562EJ1V0DS00 (1st edition)

Date Published June 2001 NS CP(K)

Printed in Japan

2001

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