DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA1742TP
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
PACKAGE DRAWING (Unit: mm)
8
5
1, 2, 3
; Source
4
; Gate
5, 6, 7, 8, 9 ; Drain
The
µ
PA1742TP is N-channel MOS FET device that
features a low on-state resistance and excellent switching
characteristics, and designed for high voltage applications
such as DC/DC converter.
1.49 ±0.21
2.0 ±0.2
2.9 MAX.
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power HSOP8
8
9
4.1 MAX.
µ
PA1742TP
5
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, unless otherwise noted. All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC) (T
C
= 25°C)
Drain Current (pulse)
Note1
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T1
Note2
250
±30
±7.0
±21
24
1.0
150
−55
to +150
7.0
4.9
7.0
V
V
A
A
W
W
°C
°C
A
mJ
A
1.1 ±0.2
•
High voltage: V
DSS
= 250 V
•
Gate voltage rating: ±30 V
•
Low on-state resistance
R
DS(on)
= 0.55
Ω
MAX. (V
GS
= 10 V, I
D
= 3.5 A)
•
Low input capacitance
C
iss
= 460 pF TYP. (V
DS
= 10 V, V
GS
= 0 V)
•
Built-in gate protection diode
•
Small and surface mount package (Power HSOP8)
1.44 TYP.
FEATURES
1
5.2
+0.17
–0.2
4
0.8 ±0.2
S
+0.10
–0.05
6.0 ±0.3
4.4 ±0.15
0.05 ±0.05
0.15
1.27 TYP.
0.40
1
+0.10
–0.05
0.10 S
0.12 M
4
EQUIVALENT CIRCUIT
Drain
Total Power Dissipation (T
C
= 25°C)
Total Power Dissipation (T
A
= 25°C)
Channel Temperature
Storage Temperature
Single Avalanche Current
Single Avalanche Energy
Note3
Note3
Note4
Note4
P
T2
T
ch
T
stg
I
AS
E
AS
I
AR
Gate
Body
Diode
Gate
Protection
Diode
Source
Repetitive Avalanche Current
Repetitive Pulse Avalanche Energy
E
AR
4.9
mJ
Notes 1.
PW
≤
10
µ
s, Duty Cycle
≤
1%
2.
Mounted on glass epoxy board of 1 inch x 1 inch x 0.8 mm
3.
Starting T
ch
= 25°C, V
DD
= 125 V, R
G
= 25
Ω,
L = 100
µ
H, V
GS
= 20
→
0 V
4.
T
ch(peak)
≤
150°C, L = 100
µ
H
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G16325EJ1V0DS00 (1st edition)
Date Published April 2003 NS CP(K)
Printed in Japan
2002
µ
PA1742TP
ELECTRICAL CHARACTERISTICS (T
A
= 25°C, unless otherwise noted. All terminals are connected.)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
Forward Transfer Admittance
Note
Note
SYMBOL
I
DSS
I
GSS
V
GS(off)
| y
fs
|
R
DS(on)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
TEST CONDITIONS
V
DS
= 250 V, V
GS
= 0 V
V
GS
= ±30 V, V
DS
= 0 V
V
DS
= 10 V, I
D
= 1 mA
V
DS
= 10 V, I
D
= 3.5 A
V
GS
= 10 V, I
D
= 3.5 A
V
DS
= 10 V
V
GS
= 0 V
f = 1 MHz
V
DD
= 125 V, I
D
= 3.5 A
V
GS
= 10 V
R
G
= 10
Ω
MIN.
TYP.
MAX.
10
±10
UNIT
µ
A
µ
A
V
S
2.5
2.5
3.5
5
0.41
460
100
45
11
9
24
8
4.5
Drain to Source On-state Resistance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Note
0.55
Ω
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
DD
= 200 V
V
GS
= 10 V
I
D
= 7.0 A
I
F
= 7.0 A, V
GS
= 0 V
I
F
= 7.0 A, V
GS
= 0 V
di/dt = 100 A/
µ
s
14
3
7
0.9
140
560
1.5
V
F(S-D)
t
rr
Q
rr
V
ns
nC
Note
Pulsed: PW
≤
800
µ
s, Duty Cycle
≤
2%
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
R
G
= 25
Ω
PG.
V
GS
= 20
→
0 V
50
Ω
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
V
DD
PG.
R
G
V
GS
R
L
V
DD
V
DS
90%
90%
10%
10%
V
GS
Wave Form
0
10%
V
GS
90%
BV
DSS
I
AS
I
D
V
DD
V
DS
V
GS
0
τ
τ
= 1
µ
s
Duty Cycle
≤
1%
V
DS
V
DS
Wave Form
0
t
d(on)
t
on
t
r
t
d(off)
t
off
t
f
Starting T
ch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= 2 mA
PG.
50
Ω
R
L
V
DD
2
Data Sheet G16325EJ1V0DS
µ
PA1742TP
TYPICAL CHARACTERISTICS (T
A
= 25°C, unless otherwise noted. All terminals are connected.)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
dT - Percentage of Rated Power - %
120
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
25
100
P
T
- Total Power Dissipation - W
0
25
50
75
100
125
150
20
80
15
60
10
40
20
5
0
0
0
25
50
75
100
125
150
175
T
C
- Case Temperature -
°C
T
C
- Case Temperature -
°C
FORWARD BIAS SAFE OPERATING AREA
100
PW = 100
µ
s
I
D(pulse)
= 21 A
I
D
- Drain Current - A
10
I
D(DC)
= 7.0 A
10 ms
1 ms
DC
1
R
DS(on)
Limited
(at V
GS
= 10 V)
0.1
T
C
= 25°C
Single pulse
0.01
0.1
1
10
100
1000
Power Dissipation Limited
V
DS
- Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
r
th(t)
- Transient Thermal Resistance -
°C/W
1000
R
th(ch-A)
= 125°C/W
100
10
R
th(ch-C)
= 5.2°C/W
1
0.1
Single pulse
R
th(ch-A)
:Mounted on glass epoxy board
(1 inch x 1inch x 0.8 mm), T
A
= 25°C
R
th(ch-C)
:T
C
= 25°C
0.01
100
µ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet G16325EJ1V0DS
3
µ
PA1742TP
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
30
Pulsed
V
GS
= 10 V
FORWARD TRANSFER CHARACTERISTICS
100
Pulsed
V
DS
= 10 V
25
I
D
- Drain Current - A
20
I
D
- Drain Current - A
10
1
T
A
= 150°C
125°C
75°C
25°C
−25°C
15
0.1
10
0.01
5
0.001
0
0
5
10
15
20
25
30
0.0001
0
5
10
15
V
DS
- Drain to Source Voltage - V
V
GS
- Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
4.5
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
| y
fs
| - Forward Transfer Admittance - S
100
T
A
=
−
25°C
25°C
75°C
125°C
150°C
V
DS
= 10 V
Pulsed
V
GS(off)
- Gate Cut-off Voltage - V
V
DS
= 10 V
I
D
= 1 mA
4
10
3.5
1
3
0.1
2.5
2
-50
-25
0
25
50
75
100
125
150
0.01
0.01
0.1
1
10
100
T
ch
- Channel Temperature -
°C
I
D
- Drain Current - A
R
DS(on)
- Drain to Source On-state Resistance -
Ω
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.1
1
10
100
Pulsed
V
GS
= 10 V
R
DS(on)
- Drain to Source On-state Resistance -
Ω
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0
2
4
6
8
10
12
14
16
18
20
I
D
= 7.0 A
3.5 A
1.4 A
Pulsed
I
D
- Drain Current - A
V
GS
- Gate to Source Voltage - V
4
Data Sheet G16325EJ1V0DS
µ
PA1742TP
R
DS(on)
- Drain to Source On-state Resistance -
Ω
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
1.5
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
1000
C
iss
, C
oss
, C
rss
- Capacitance - pF
V
GS
= 10 V
Pulsed
1.25
C
iss
1
I
D
= 7.0 A
100
0.75
3.5 A
0.5
C
oss
10
C
rss
V
GS
= 0 V
f = 1 MHz
1
0.25
0
-50
-25
0
25
50
75
100
125
150
175
0.1
1
10
100
1000
T
ch
- Channel Temperature - °C
V
DS
- Drain to Source Voltage - V
SWITCHING CHARACTERISTICS
100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
250
15
I
D
= 7.0 A
200
V
DD
= 200 V
125 V
62.5 V
12
t
d(off)
t
f
10
t
d(on)
t
r
150
9
100
V
GS
50
V
DS
0
6
3
1
0.1
1
10
100
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
I
D
- Drain Current - A
Q
G
- Gate Charge - nC
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
100
1000
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
t
rr
- Reverse Recovery Time - ns
di/dt = 100 A/µs
V
GS
= 0 V
I
F
- Diode Forward Current - A
Pulsed
V
GS
= 0 V
10
100
1
10
0.1
0.01
0
0.25
0.5
0.75
1
1.25
1.5
1
0.1
1
10
100
V
F(S-D)
- Source to Drain Voltage - V
I
F
- Diode Forward Current - A
Data Sheet G16325EJ1V0DS
5
V
GS
- Gate to Source Voltage - V
t
d(on)
, t
r
, t
d(off)
, t
f
- Switching Time - ns
V
DD
= 125 V
V
GS
= 10 V
R
G
= 0
Ω
V
DS
- Drain to Source Voltage - V
京公网安备 11010802033920号
EEWORLD
