®
X28C010
Data Sheet
May 11, 2005
FN8105.0
5 Volt, Byte Alterable EEPROM
The Intersil X28C010 is a 128K x 8 EEPROM, fabricated
with Intersil's proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable non-
volatile memories, the X28C010 is a 5V only device. The
X28C010 features the JEDEC approved pin out for byte-
wide memories, compatible with industry standard
EEPROMs.
The X28C010 supports a 256-byte page write operation,
effectively providing a 19µs/byte write cycle and enabling the
entire memory to be typically written in less than 2.5
seconds. The X28C010 also features DATA Polling and
Toggle Bit Polling, system software support schemes used to
indicate the early completion of a write cycle. In addition, the
X28C010 supports Software Data Protection option.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Data retention is specified to
be greater than 100 years.
Features
• Access time: 120ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or V
PP
control
circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low power CMOS
- Active: 50mA
- Standby: 500µA
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Write
™
cell
- Endurance: 100,000 write cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
Pinouts
PLCC
LCC
NC
VCC
A 12
A 15
A 16
WE
NC
EXTENDED LCC
A12
A15
A16
NC
VCC
4 3 2
1
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
A7
A6
A5
A4
A3
A2
A1
A0
I/O 0
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
30
I/O1
I/O2
VSS
I/O3
WE
NC
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
CERDIP
Flat Pack
SOIC (R)
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X28C010
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PGA
I/O0
I/O2
I/O 3
I/O5
I/O6
15
17
19
21
22
A1
13
A2
12
A4
10
A6
A12
6
5
A
16
A0
14
A3
11
9
A5
A7
A15
2
NC
3
NC
VCC
NC
36
34
NC
1
WE
35
CE
I/O1
VSS
I/O4
I/O7
16
18
20
23
24
OE
A10
26
25
32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
X28C010
(Bottom View)
A11
27
A8
29
NC
32
NC
33
A9
28
A 13
30
A 14
31
32 31
54 3 2
29
1
6
28
7
27
26
8
X28C010
25
9
(Top View)
24
10
11
23
12
22
13
15 16 17 18 19 20 21
14
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
X28C010
(Top View)
8
7
14 15 16 17 18 19 20
I/O4
I/O5
I/O6
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
TSOP
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
4
X28C010
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28C010
Ordering Information
PART NUMBER
X28C010D
X28C010D-12
X28C010D-15
X28C010DI
X28C010DI-12
X28C010DI-15
X28C010DI-
15C7681
X28C010DM
X28C010DM-12
X28C010DMB-12
X28C010DMB-
12C7309
X28C010DMB-
12C7729
X28C010DMB-15
X28C010DMB-
15C7762
X28C010DMB-20
X28C010DMC7237
X28C010FI-12
X28C010FI-15
X28C010FI-
15C1009
X28C010FI-20
X28C010FI-25
X28C010FM
X28C010FM-12
X28C010FMB-15
X28C010FMB-
15C7619
X28C010FMB-
15C7808
X28C010K-25
X28C010KM-12
X28C010KM-25
X28C010KM-
25C7237
X28C010KMB-15
ACCESS
TIME
-
120ns
150ns
-
120ns
150ns
150ns
-
120ns
120ns
120ns
120ns
150ns
150ns
200ns
-
120ns
150ns
150ns
200ns
250ns
-
120ns
150ns
150ns
150ns
250ns
120ns
250ns
250ns
150ns
PACKAGE
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
36-Ld Pin Grid
Array
36-Ld Pin Grid
Array
36-Ld Pin Grid
Array
36-Ld Pin Grid
Array
36-Ld Pin Grid
Array
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
MIL-STD-883
0 to 70
-55 to +125
-55 to +125
-55 to +125
MIL-STD-883
X28C010RMB-25
250ns
TEMP
RANGE (°C)
0 to 70
0 to 70
0 to 70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
MIL-STD-883
MIL-STD-883
MIL-STD-883
MIL-STD-883
X28C010RI-
20C7168
X28C010RI-
20C7975
X28C010RI-20T1
X28C010RI-
20T1C7168
X28C010RM-15
200ns
200ns
200ns
200ns
150ns
X28C010RI-20
200ns
X28C010NMB-15
X28C010NMB-
15C7309
X28C010RI-12
150ns
150ns
120ns
Ordering Information
(Continued)
PART NUMBER
X28C010NM-12
X28C010NM-15
X28C010NMB-12
ACCESS
TIME
120ns
150ns
120ns
PACKAGE
32-Ld Extended
LCC
32-Ld Extended
LCC
32-Ld Extended
LCC
32-Ld Extended
LCC
32-Ld Extended
LCC
32-Ld Ceramic
SOIC (Gull Wing)
32-Ld Ceramic
SOIC (Gull Wing)
32-Ld Ceramic
SOIC (Gull Wing)
32-Ld Ceramic
SOIC (Gull Wing)
32-Ld Ceramic
SOIC (Gull Wing)
32-Ld Ceramic
SOIC (Gull Wing)
32-Ld Ceramic
SOIC (Gull Wing)
TEMP
RANGE (°C)
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
MIL-STD-883
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-55 to +125
MIL-STD-883
32-Ld Ceramic
SOIC (Gull Wing)
2
FN8105.0
May 11, 2005
X28C010
Block Diagram
A
8
-A
16
X Buffers
Latches and
Decoder
1Mbit
EEPROM
Array
A
0
-A
7
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
CE
OE
WE
V
CC
V
SS
Control
Logic and
Timing
I/O
0
-I/O
7
Data Inputs/Outputs
Pin Descriptions
Addresses (A
0
-A
16
)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers,
and is used to initiate read operations.
Data In/Data Out (I/O
0
-I/O
7
)
Data is written to or read from the X28C010 through the I/O
pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010.
Pin Names
SYMBOL
A
0
-A
16
I/O
0
-I/O
7
WE
CE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C010 supports both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs
last. Similarly, the data is latched internally by the rising edge
of either CE or WE, whichever occurs first. A byte write
operation, once initiated, will automatically continue to
completion, typically within 5ms.
3
FN8105.0
May 11, 2005
X28C010
Page Write Operation
The page write feature of the X28C010 allows the entire
memory to be written in 5 seconds. Page write allows two to
two hundred fifty-six bytes of data to be consecutively written
to the X28C010 prior to the commencement of the internal
programming cycle. The host can fetch data from another
device within the system during a page write operation
(change the source address), but the page address (A
8
through A
16
) for each subsequent valid write cycle to the part
during this operation must be the same as the initial page
address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to two hundred fifty six bytes in the
same manner as the first byte was written. Each successive
byte load cycle, started by the WE HIGH to LOW transition,
must begin within 100µs of the falling edge of the preceding
WE. If a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively the page write window is infinitely wide,
so long as the host continues to access the device within the
byte load cycle time of 100µs.
I/O
DP
TB
5
4
3
2
1
0
Reserved
Toggle Bit
DATA Polling
FIGURE 1. STATUS BIT ASSIGNMENT
DATA Polling (I/O
7
)
The X28C010 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28C010, eliminating additional
interrupt inputs or external hardware. During the internal
programming cycle, any attempt to read the last byte written
will produce the complement of that data on I/O
7
(i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true data.
Note: If the X28C010 is in the protected state, and an illegal
write operation is attempted, DATA Polling will not operate.
Toggle Bit (I/O
6
)
The X28C010 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle, I/O
6
will toggle from HIGH to LOW and
LOW to HIGH on subsequent attempts to read the device.
When the internal cycle is complete the toggling will cease
and the device will be accessible for additional read or write
operations.
Write Operation Status Bits
The X28C010 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown
in Figure 1.
DATA Polling I/O
7
WE
Last
Write
CE
OE
V
IH
I/O
7
HIGH Z
V
OL
V
OH
X28C010
Ready
A
n
A
n
A
n
A
n
A
0
-A
14
A
n
A
n
A
n
FIGURE 2. DATA POLLING BUS SEQUENCE
4
FN8105.0
May 11, 2005
X28C010
DATA Polling can effectively halve the time for writing to the
X28C010. The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 3 illustrates one method of implementing the routine.
Write Data
Writes
Complete?
No
Yes
Save Last Data
and Address
Read Last
Address
IO
7
Compare?
Yes
No
X28C010
Ready
FIGURE 3. DATA POLLING SOFTWARE FLOW
The Toggle Bit I/O
6
WE
Last
Write
CE
OE
I/O
6
V
OH
*
V
OL
HIGH Z
*
X28C010
Ready
* Beginning and ending state of I/O
6
will vary
FIGURE 4. TOGGLE BIT BUS SEQUENCE
5
FN8105.0
May 11, 2005
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