531SB557M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531SB557M000DG

531SB557M000DG: DescriptionLVDS Output Clock Oscillator, 557MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531SB557M000DG Overview

LVDS Output Clock Oscillator, 557MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531SB557M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	557 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Pulse therapy circuit

Spike Peak Measurement Circuit

Using photoelectric thyristor as overvoltage protection circuit

Optocoupler TIL102/TIL103 connection equivalent circuit

Frequency multiplication and division circuit diagram

Circuit that uses photoconductive emitting elements to detect tiny displacements

What is the difference between MAX232 and MAX487?: An RS232 and an RS485 interface are both used for transceivers and level logic conversion, but these are purely theoretical functions. I just want to know what they can do in practice without too many...; xinyi7200 Embedded System

CAN chip mcp2515: Friends who plan to use the mcp2515 chip can refer to the following...; delay PCB Design

Fujitsu Ferroelectric Random Access Memory (FRAM) Theme Pavilion is now online. Visit to learn more and find surprises!: [size=4] [/size] [size=4] {:1_102:}[/size][size=4]Today,[/size][size=4]Fujitsu Ferroelectric Random Access Memory FRAM Theme Pavilion is online,[/size][size=4] [/size] [size=4] [/size][size=4] Welcome...; EEWORLD社区 Robotics Development

[liklon plays with GD32F350] 1. Unboxing and testing demo: Board picture:1. Download materials (go to [url=https://www.eeworld.com.cn/huodong/Gigadevice_GD32F350Contest_201808/index.html#5]Activity homepage download options[/url]):2. Test demo The file path i...; liklon GD32 MCU

TI Power Design Tips 15: Welcome to Power Design Tips! With today's emphasis on more efficient, lower cost power solutions, we created this column to provide helpful tips on a variety of power management topics. This column i...; trevor Analogue and Mixed Signal

People say it takes 5 years to get into simulation?: What do you think? Personally, I don’t think 5 years is long....; 幸福的娃 Analog electronics

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components