White Electronic Designs
256MB- 32Mx72 DDR SDRAM REGISTERED
FEATURES
Double-data-rate architecture
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
JEDEC standard 184 pin DIMM package
Power Supply: 2.5V ± 0.25V
WED3EG7234S-D3
FINAL
DESCRIPTION
The WED3DG7234S is a 32Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR
SDRAM component. The module consists of eighteen
32Mx4 DDR SDRAMs in 66 pin TSOP package
mounted on a 184 Pin FR4 substrate.
Synchronous design allows precise cycle control
with the use of system clock. Data I/O transactions
are possible on both edges and Burst Lenths allow
the same device to be useful for a variety of high
bandwidth, high performance memory system
applications.
*
This datasheet describes a product that may or may not be under development
and is subject to change or cancelled without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2002
Rev. # 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Symbol
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
RESET#
V
SS
DQ8
DQ9
DQS1
V
DDQ
*CK1
*CK1#
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
Pin
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Symbol
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DDQ
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
V
DD
*CS2#
DQ48
DQ49
V
SS
*CK2#
*CK2
V
DDQ
DQS6
DQ50
DQ51
V
SS
V
DDIQ
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NA
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
Symbol
V
SS
DQ4
DQ5
V
DDQ
DQS9
DQ6
DQ7
V
SS
NC
NC
*A13
V
DDQ
DQ12
DQ13
DQS10
V
DD
DQ14
DQ15
*CKE1
V
DDQ
*BA2
DQ20
A12
V
SS
DQ21
A11
DQS11
V
DD
DQ22
A8
DQ23
V
SS
A6
DQ28
DQ29
V
DDQ
DQS12
A3
DQ30
V
SS
DQ31
CB4
CB5
V
DDQ
CK0
CK0#
Pin
139
140
141
V
DD
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Symbol
V
SS
DQS17
A10
CB6
V
DDQ
CB7
V
SS
DQ36
DQ37
V
DD
DQS13
DQ38
DQ39
V
SS
DQ44
RAS#
DQ45
V
DDQ
CS#0
*CS1#
DQS14
V
SS
DQ46
DQ47
*CS3#
V
DDQ
DQ52
DQ53
NC
V
DD
DQS15
DQ54
DQ55
V
DDQ
NC
DQ60
DQ61
V
SS
DQS16
DQ62
DQ63
V
DDQ
SA0
SA1
SA2
V
DD
SPD
WED3EG7234S-D3
FINAL
PIN NAMES
A0 – A12
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS17
CK0
CK0#
CKE0#
CS0#
RAS#
CAS#
WE#
V
DD
V
DDQ
V
SS
V
REF
V
DDSPD
SDA
SCL
SA0-SA2
V
DDID
NC
RESET
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
Data Strobe Input/Output
Clock Input
Clock Input
Clock Enable Input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
Power Supply (2.5V)
Power Supply for DQS (2.5V)
Ground
Power Supply for Reference
Serial EEPROM Power Supply
(2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
V
DD
Identification Flag
No Connect
Reset Enable
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2002
Rev. # 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
VSS
RS0#
DQS0
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
WED3EG7234S-D3
FINAL
DQS9
D0
DQS
3
2
1
0
CS#
DM
D9
DQS1
DQ8
DQ9
DQ10
DQ11
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS10
DQ12
DQ13
DQ14
DQ15
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
D1
D10
DQS2
DQ16
DQ17
DQ18
DQ19
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
DQS11
DQ20
DQ21
DQ22
DQ23
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
D2
D11
DQS3
DQ24
DQ25
DQ26
DQ27
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
DQS12
DQ28
DQ29
DQ30
DQ31
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
D3
D12
DQS4
DQ32
DQ33
DQ34
DQ35
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS13
DQ36
DQ37
DQ38
DQ39
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
CK0
D13
S
D4
PLL
CK0#
R
DM
DQS5
DQ40
DQ41
DQ42
DQ43
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
DQS14
DQ44
DQ45
DQ46
DQ47
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
D5
D14
DQS6
DQ48
DQ49
DQ50
DQ51
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS15
DQ52
DQ53
DQ54
DQ55
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
Serial PD
SCL
WP
A0
A1
SA1
A2
SA2
SD
D6
D15
DQS7
DQ56
DQ57
DQ58
DQ59
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
DQS16
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
DQS
3
2
1
0
CS#
DM
SA0
D7
D16
V
DDSPD
V
DD
/V
DDQ
CS#
DM
DQS8
CB0
CB1
CB2
CB3
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS17
CB4
CB5
CB6
CB7
DQS
I/O 3
I/O 2
I/O 1
I/O 0
SPD
D0 - D
D0 - D
D8
D17
VREF
V
SS
D0 - D
D0 - D
CS0#
BA0-BAN
A0-A12
RAS#
CAS#
CKE0
WE#
PCK
PCK#
R
E
G
I
S
T
E
R
RS0A#
RS0B#
RBA0 - RBAn
RA0 #-RA12
RRAS
RCAS
RCKE0A
RCK#E0B
RWE
RESET#
BA0-BAn: SDRAMsDQ0- D17
A0 -An : SDRAMsD0 - D17
RAS# :SDRAMsD0 - D17
CAS#: SDRAMsDQ0- D17
CKE : SDRAMsD0 - D8
CKE: SDRAMsD9 - D17
WE#:SDRAMsD0 - D17
Notes:
1. DQ-to-I/O wiring is shown as recom
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships m
be maintained as shown.
3. DQ, DQS resistors: 22 Ohms.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2002
Rev. # 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Note:
WED3EG7234S-D3
FINAL
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
27
50
Units
V
V
°C
W
mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
(TA = 0 to 70C, V
DD
= 2.5V +\-0.2V)
Parameter
Supply Voltage
Supply Voltage
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
IH
V
IL
V
OH
V
OL
Min
2.3
2.3
1.15
1.15
V
REF
+0.15
-0.3
V
TT
+0.76
—
Max
2.7
2.7
1.35
1.35
V
DDQ
+0.3
V
REF
+0.15
—
V
TT
-0.76
Unit
V
V
V
V
V
V
V
V
CAPACITANCE
(T
A
= 23°C, f = 1MHz, V
DD
= 3.3V, V
REF
=1.4V ± 200mV)
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0, CK0#)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
Symbol
C
IN
1
C
IN
2
C
IN
3
C
IN
4
C
IN
5
C
IN
6
C
IN
7
C
OUT
C
OUT
Min
-
-
-
-
-
-
-
-
-
Max
12
12
12
12
11
15
12
15
15
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2002
Rev. # 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3EG7234S-D3
FINAL
IDD SPECIFICATIONS AND TEST CONDITIONS
(Recommended operating conditions, TA = 0 to 70C, V
DDQ
= 2.5V+\-0.2V, V
DD
= 2.5V +\-0.2V)
Parameter
Symbol
Conditions
One device bank; Active = Precharge;
TRC=TRC(MIN); TCK=TCK
(MIN); DQ, DM and DQS inputs changing
once per clock cycle; Address and control
inputs changing once every two cycles.
One device banks; Active-Read-Precharge;
Burst = 2; TRC=TRC(MIN); TCK=TCK
(MIN); lout=0mA; Address and control inputs
changing once per clock cycle.
All device bank idle; Power-down mode;
TCK=TCK(MIN); CKE=(low)
CS# = High; All device banks idle;
TCK=TCK(MIN); CKE = high; Address and
other control inputs changing once per clock
cycle. Vin = Vref for DQ, DQS and DM.
One device bank active; Power-down mode;
TCK(MIN); CKE=(low)
CS# = High; CKE = High; One device bank;
Active-Precharge; TRC=TRAS(MAX);
TCK=TCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle
Burst = 2; Reads; Continous burst; Once
device bank active; Address and control
inputs changing once per clock cycle;
TCK=TCK(MIN); I
OUT
=0mA
Burst=2; Writes; Continous burst; Once
device bank active; Address and control
inputs changing once per clock cycle;
TCK=TCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
TRC=TRC(MIN)
CKE < 0.2V
Four bank interleaving Reads (BL=4) with
auto precharge with TRC=TRC(MIN);
TCK=TCK(MIN); Address and control input
change only during Active Read or Write
commands.
DDR266@CL=2
Max
DDR266@CL=2.5
Max
DDR200@CL=2
Max
Units
Operating Current
I
DD0
2660
2660
2470
mA
Operating Current
Precharge Power-
Down Standby Current
dle Standby Current
Active Power-Down
Standby Current
I
DD1
2980
2980
2800
mA
I
DD2P
1130
1130
1120
mA
I
DD2F
1460
1460
1400
mA
I
DD3P
1620
1620
1520
mA
Active Standby Current
I
DD3N
1950
1950
1790
mA
Operating Current
I
DD4R
3120
3120
2750
mA
Operating Current
I
DD4W
3240
3240
2790
mA
Auto Refresh Current
Self Refresh Current
I
DD5
I
DD6
4080
1140
4080
1140
4080
1140
mA
mA
Operating Current
I
DD7A
5890
5890
4840
mA
* Module I
DD
was calculated on the basis of component I
DD
and can be different measured according to DQ loading cap.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2002
Rev. # 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
京公网安备 11010802033920号
EEWORLD
