DATA SHEET
COMPOUND TRANSISTOR
µ
PA104
HIGH FREQUENCY NPN TRANSISTOR ARRAY
FEATURES
•
9 GHz CONFIGURABLE TRANSISTOR BASED OR/NOR CIRCUITRY
•
OUTSTANDING h
FE
LINEARITY
•
TWO PACKAGE OPTIONS:
µ
PA104B:
Studded ceramic package provides superior thermal dissipation
µ
PA104G:
Reduced circuit size due to 14-pin plastic SOP package for surface mounting
•
EXCELLENT FOR ANALOG ADDITIONS & FORMATION OF 2-INPUT OR/NOR GATES
DESCRIPTION AND APPLICATIONS
The
µ
PA104 is a user-configurable, Si bipolar transistor array for formation of high speed OR/NOR gates. Its
internal transistor configuration and external connection options allow the user considerable flexibility in its
application. Its high gain bandwidth product (f
T
= 9 GHz) make it applicable for electro-optical, signal processing,
cellular telephone systems, instrumentation, and high speed gigabit logic circuits.
ORDERING INFORMATION
PART NUMBER
PACKAGE
14-pin ceramic package
14-pin plastic SOP (225 mil)
µ
PA104B-E1
µ
PA104G-E1
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
SYMBOLS
V
CBO
*
V
CEO
*
V
EBO
*
I
C
*
P
T
PARAMETERS
Collector to Base Voltage
Collector to Emitter Voltage
Emitter to Base Voltage
Collector Current
Power Dissipation
µ
PA104B
µ
PA104G
Junction Temperature
µ
PA104B
µ
PA104G
Storage Temperature
µ
PA104B
µ
PA104G
UNITS
V
V
V
mA
mW
mW
°C
°C
°C
°C
RATINGS
15
6
2.5
40
650
350
200
125
–55 to +200
–55 to +125
T
J
T
STG
*
Absolute maximum ratings for each transistor.
Caution electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. P10709EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1995, 1999
µ
PA104
PACKAGE DIMENSIONS
(UNIT: mm)
µ
PA104B
14 PIN CERAMIC PACKAGE
φ
0.8
TOP VIEW
0.35
6.2
1.27
5.0 MAX.
2. 7
MAX.
SIDE VIEW
4.5 MIN.
0.08
2.3 MIN.
φ
1.6
BOTTOM VIEW
1.8
3.0
µ
PA104G
14 PIN PLASTIC SOP (225 mil)
14
8
detail of lead end
3°
–3°
1
10.2
±
0.26
1.49
7
+7°
6.55
±
0.2
4.38
±
0.1
1.1
±
0.16
0.6
±
0.2
1.27
0.40
+0.10
–0.05
0.1
±
0.1
1.59
+0.21
–0.20
NOTE
Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
0.10
M
1.42 MAX
0.15
–0.05
+0.10
0.10
See connection diagram for description of leads.
2
Data Sheet P10709EJ2V0DS00
µ
PA104
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified T
A
= +25 ˚C
µ
PA104B,
µ
PA104G common)
SYMBOLS
I
CBO
I
EBO
h
FE
C
CB
C
EB
C
CS
f
T
PARAMETERS AND CONDITIONS
Collector Cutoff Current at V
CB
= 5 V, I
E
= 0 (Q1 thru Q6)
Emitter Cutoff Current at V
EB
= 1 V, I
C
= 0 (Q4 thru Q6)
Direct Current Amplification at V
CE
= 3 V, I
C
= 5 mA (Q4 and Q6)
Collector to Base Capacitance at V
CB
= 3 V, f = 1 MHz (Q3, Q5, Q6)
Emitter to Base Capacitance at V
EB
= 0, f = 1 MHz (Q4 thru Q6)
Collector/Substrate Capacitance, V
CS
= 3 V, f = 1 MHz (Q3, Q5, Q6)
Gain Bandwidth Product* at V
CE
= 3 V, I
C
= 10 mA
pF
pF
pF
GHz
UNITS
MIN.
TYP.
MAX.
1.0
1.0
40
100
0.9
1.4
1.4
9.0
250
1.8
2.8
2.8
µ
A
µ
A
*
Measured by installing a single transistor in a Micro-X package: the value shown is a reference value.
CONNECTION DIAGRAM
(Top View)
µ
PA104B
14
13
12
11
10
9
8
Q
6
Q
5
Q
1
SUB
Q
4
Q
2
Q
3
1
2
3
4
5
6
7
µ
PA104G
14
13
12
11
10
9
8
Q
5
Q
1
Q
2
Q
3
Q
6
Q
4
1
2
3
4
5
6
7
Note:
Substrate should be connected to the lowest voltage point in order to prevent latch-up.
Data Sheet P10709EJ2V0DS00
3
µ
PA104
TYPICAL PERFORMANCE CHARACTERISTICS
(T
A
= +25
°C)
COLLECTOR CURRENT vs.
COLLECTOR TO EMITTER VOLTAGE
10
100
Collector Current, I
C
(mA)
8
80
60
40
I
B
= 20
µ
A
Collector Current, I
C
(mA)
200
100
50
20
10
5
2
1
0.5
V
CE
= 3 V
0
0
1
2
3
4
5
Collector to Emitter Voltage, V
CE
(V)
0.1
0
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
Base to Emitter Voltage, V
BE
(V)
COLLECTOR CURRENT vs.
BASE TO EMITTER VOLTAGE
6
4
2
DC CURRENT GAIN vs.
COLLECTOR CURRENT
Gain Bandwidth Product, f
T
(GHz)
1000
12
GAIN BANDWIDTH PRODUCT vs.
COLLECTOR CURRENT
DC Current Gain, h
FE
10
V
CE
= 5 V
200
V
CE
= 3 V
100
50
20
10
0.5
1
2
5
10 20
Collector Current, I
C
(mA)
50
8
3V
6
1V
4
1
2
5
10
20
Collector Current, I
C
(mA)
50
GAIN AND NOISE FIGURE OF
INDIVIDUAL TRANSISTOR
20
V
CC
= 3 V
f = 1 GHz
GAIN
Gain (dB)
6
10
4
Noise Figure, NF (dB)
8
NF
0
2
1
2
5
10
20
50 100
Collector Current, I
C
(mA)
0
4
Data Sheet P10709EJ2V0DS00
µ
PA104
TYPICAL APPLICATION
A
B
A+B
OR
A
B
V
CC
(+2 V)
100
Ω
115
Ω
300
Ω
OR
50
Ω
50 KΩ
50 KΩ 47
Ω
100
Ω
1.5 KΩ
2.8 KΩ
V
EE
(–3.2 V)
V
BB
(–1.6 V)
+1.1 V
IN
50 %
t++
OUT (OR)
50 %
50 %
t––
50 %
tf
90 %
10 %
t++ = 500 psec.
t–– = 250 psec.
t
R
+0.3 V
tf = 500 psec.
t
R
= 750 psec.
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
Data Sheet P10709EJ2V0DS00
5
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