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IS61LP12832-200TQI

Description
Cache SRAM, 128KX32, 3.1ns, CMOS, PQFP100, TQFP-100
Categorystorage    storage   
File Size121KB,15 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
Download Datasheet Parametric Compare View All

IS61LP12832-200TQI Overview

Cache SRAM, 128KX32, 3.1ns, CMOS, PQFP100, TQFP-100

IS61LP12832-200TQI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIntegrated Silicon Solution ( ISSI )
Parts packaging codeQFP
package instructionTQFP-100
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time3.1 ns
Maximum clock frequency (fCLK)200 MHz
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density4194304 bit
Memory IC TypeCACHE SRAM
memory width32
Number of functions1
Number of terminals100
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply2.5/3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.02 A
Minimum standby current3.14 V
Maximum slew rate0.31 mA
Maximum supply voltage (Vsup)3.63 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
IS61LP12832
IS61LP12836
128K x 32, 128K x 36 SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Linear burst sequence control using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• 2.5V I/O supply voltage
• Industrial temperature available
ISSI
®
PRELIMINARY INFORMATION
MAY 2001
DESCRIPTION
The
ISSI
IS61LP12832 and IS61LP12836 is a high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 131,072
words by 32 bits and 36 bits, fabricated with
ISSI
's
advanced CMOS technology. The device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls
DQc,
BW4
controls DQd, conditioned by
BWE
being
LOW. A LOW on
GW
input would cause all bytes to be
written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-200
3.1
5
200
-166
3.5
6
166
Units
ns
ns
MHz
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
05/10/01
Rev. 00A
1

IS61LP12832-200TQI Related Products

IS61LP12832-200TQI IS61LP12832-166BI IS61LP12832-166B IS61LP12832-166TQI IS61LP12836-166B IS61LP12836-166BI IS61LP12836-166TQI IS61LP12832-200B
Description Cache SRAM, 128KX32, 3.1ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 128KX32, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119 Cache SRAM, 128KX32, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119 Cache SRAM, 128KX32, 3.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119 Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119 Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, TQFP-100 Cache SRAM, 128KX32, 3.1ns, CMOS, PBGA119, PLASTIC, BGA-119
Is it lead-free? Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible incompatible incompatible incompatible
Parts packaging code QFP BGA BGA QFP BGA BGA QFP BGA
package instruction TQFP-100 PLASTIC, BGA-119 PLASTIC, BGA-119 TQFP-100 PLASTIC, BGA-119 PLASTIC, BGA-119 TQFP-100 PLASTIC, BGA-119
Contacts 100 119 119 100 119 119 100 119
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant
ECCN code 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
Maximum access time 3.1 ns 3.5 ns 3.5 ns 3.5 ns 3.5 ns 3.5 ns 3.5 ns 3.1 ns
Maximum clock frequency (fCLK) 200 MHz 166 MHz 166 MHz 166 MHz 166 MHz 166 MHz 166 MHz 200 MHz
I/O type COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 code R-PQFP-G100 R-PBGA-B119 R-PBGA-B119 R-PQFP-G100 R-PBGA-B119 R-PBGA-B119 R-PQFP-G100 R-PBGA-B119
JESD-609 code e0 e0 e0 e0 e0 e0 e0 e0
length 20 mm 22 mm 22 mm 20 mm 22 mm 22 mm 20 mm 22 mm
memory density 4194304 bit 4194304 bit 4194304 bit 4194304 bit 4718592 bit 4718592 bit 4718592 bit 4194304 bit
Memory IC Type CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM
memory width 32 32 32 32 36 36 36 32
Number of functions 1 1 1 1 1 1 1 1
Number of terminals 100 119 119 100 119 119 100 119
word count 131072 words 131072 words 131072 words 131072 words 131072 words 131072 words 131072 words 131072 words
character code 128000 128000 128000 128000 128000 128000 128000 128000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 85 °C 70 °C 85 °C 70 °C 85 °C 85 °C 70 °C
Minimum operating temperature -40 °C -40 °C - -40 °C - -40 °C -40 °C -
organize 128KX32 128KX32 128KX32 128KX32 128KX36 128KX36 128KX36 128KX32
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LQFP BGA BGA LQFP BGA BGA LQFP BGA
Encapsulate equivalent code QFP100,.63X.87 BGA119,7X17,50 BGA119,7X17,50 QFP100,.63X.87 BGA119,7X17,50 BGA119,7X17,50 QFP100,.63X.87 BGA119,7X17,50
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form FLATPACK, LOW PROFILE GRID ARRAY GRID ARRAY FLATPACK, LOW PROFILE GRID ARRAY GRID ARRAY FLATPACK, LOW PROFILE GRID ARRAY
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) 240 240 240 240 240 240 240 240
power supply 2.5/3.3 V 2.5/3.3 V 2.5/3.3 V 2.5/3.3,3.3 V 2.5,3.3 V 2.5,3.3 V 2.5/3.3,3.3 V 2.5/3.3 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.6 mm 2.41 mm 2.41 mm 1.6 mm 2.41 mm 2.41 mm 1.6 mm 2.41 mm
Maximum standby current 0.02 A 0.02 A 0.015 A 0.02 A 0.015 A 0.02 A 0.02 A 0.015 A
Minimum standby current 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V 3.14 V
Maximum slew rate 0.31 mA 0.3 mA 0.29 mA 0.3 mA 0.29 mA 0.3 mA 0.3 mA 0.3 mA
Maximum supply voltage (Vsup) 3.63 V 3.63 V 3.63 V 3.63 V 3.63 V 3.63 V 3.63 V 3.63 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL COMMERCIAL INDUSTRIAL COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING BALL BALL GULL WING BALL BALL GULL WING BALL
Terminal pitch 0.65 mm 1.27 mm 1.27 mm 0.65 mm 1.27 mm 1.27 mm 0.65 mm 1.27 mm
Terminal location QUAD BOTTOM BOTTOM QUAD BOTTOM BOTTOM QUAD BOTTOM
Maximum time at peak reflow temperature 30 30 30 30 30 30 30 30
width 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm
Maker Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) - Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )

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