IS61LP12832
IS61LP12836
128K x 32, 128K x 36 SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Linear burst sequence control using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
• 2.5V I/O supply voltage
• Industrial temperature available
ISSI
®
PRELIMINARY INFORMATION
MAY 2001
DESCRIPTION
The
ISSI
IS61LP12832 and IS61LP12836 is a high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 131,072
words by 32 bits and 36 bits, fabricated with
ISSI
's
advanced CMOS technology. The device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls
DQc,
BW4
controls DQd, conditioned by
BWE
being
LOW. A LOW on
GW
input would cause all bytes to be
written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-200
3.1
5
200
-166
3.5
6
166
Units
ns
ns
MHz
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
05/10/01
Rev. 00A
1
IS61LP12832
IS61LP12836
BLOCK DIAGRAM
MODE
Q0
A0'
ISSI
CLK
A0
®
CLK
BINARY
COUNTER
ADV
ADSC
ADSP
CE
CLR
Q1
A1'
A1
128K x 32/128K x 36
MEMORY ARRAY
15
17
A16-A0
17
D
Q
ADDRESS
REGISTER
CE
CLK
32 or 36
32 or 36
GW
BWE
BW4
DQd
BYTE WRITE
REGISTERS
CLK
D
Q
BW3
DQc
Q
BYTE WRITE
REGISTERS
CLK
D
BW2
DQb
BYTE WRITE
REGISTERS
CLK
D
Q
BW1
DQa
Q
BYTE WRITE
REGISTERS
D
CLK
CE
CE2
CE2
D
Q
4
ENABLE
REGISTER
CE
CLK
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
OE
32 or 36
DQ[31:0]
or
DQ[35:0]
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
05/10/01
IS61LP12832
IS61LP12836
PIN CONFIGURATION
119-pin PBGA (Top View)
1
A
VCCQ
B
NC
C
NC
D
DQc1
E
DQc2
F
VCCQ
G
DQc5
H
DQc7
J
VCCQ
K
DQd1
L
DQd4
M
VCCQ
N
DQd6
P
DQd8
R
NC
T
NC
U
VCCQ
NC
NC
A10
NC
A11
NC
A14
NC
NC
NC
ZZ
VCCQ
A5
MODE
VCC
NC
A13
NC
NC
GND
A0
GND
NC
DQa1
DQd7
GND
A1
GND
DQa3
DQa2
DQd5
GND
DQd3
DQd2
GND
BW4
CLK
NC
BWE
GND
BW1
GND
DQa7
DQa5
DQa4
DQa8
DQa6
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
DQc8
GND
DQc6
DQc4
GND
BW3
DQc3
GND
NC
GND
NC
CE
OE
ADV
GW
GND
GND
GND
BW2
GND
NC
DQb6
DQb5
DQb4
DQb2
DQb8
DQb7
VCCQ
DQb3
DQb1
A7
A2
VCC
A12
A15
NC
CE2
A3
A6
A4
2
3
4
5
6
7
ISSI
100-Pin TQFP
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
®
ADSP
ADSC
A8
A9
A16
CE2
VCCQ
NC
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
128K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
CE, CE2,
CE2
OE
DQa-DQd
MODE
V
CC
GND
V
CCQ
ZZ
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: 2.5V
Snooze Enable
A2-A16
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
05/10/01
Rev. 00A
3
IS61LP12832
IS61LP12836
PIN CONFIGURATION
119-pin PBGA (Top View)
1
A
VCCQ
B
NC
C
NC
D
DQc1
E
DQc2
F
VCCQ
G
DQc5
H
DQc7
J
VCCQ
K
DQd1
L
DQd4
M
VCCQ
N
DQd6
P
DQd8
R
NC
T
NC
U
VCCQ
NC
NC
NC
NC
NC
VCCQ
NC
A10
A11
A14
NC
ZZ
A5
MODE
VCC
NC
A13
NC
DQPd
GND
A0
GND
DQPa
DQa1
DQd7
GND
A1
GND
DQa3
DQa2
DQd5
GND
DQd3
DQd2
GND
BW4
CLK
NC
BWE
GND
BW1
GND
DQa7
DQa5
DQa4
DQa8
DQa6
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
DQc8
GND
DQc6
DQc4
GND
BW3
DQc3
GND
DQPc
GND
NC
CE
OE
ADV
GW
GND
GND
GND
BW2
GND
DQPb
DQb6
DQb5
DQb4
DQb2
DQb8
DQb7
VCCQ
DQb3
DQb1
A7
A2
VCC
A12
A15
NC
CE2
A3
A6
A4
2
3
4
5
6
7
ISSI
100-Pin TQFP
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
®
ADSP
ADSC
A8
A9
A16
CE2
VCCQ
NC
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
DQPa
128K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
CE, CE2,
CE2
OE
DQa-DQd
MODE
V
CC
GND
V
CCQ
ZZ
DQPa-DQPd
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: 2.5V
Snooze Enable
Parity Data I/O
A2-A16
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00A
05/10/01
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
IS61LP12832
IS61LP12836
TRUTH TABLE
Operation
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Snooze Mode
Address
Used
None
None
None
None
None
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
—
CE
H
L
L
X
X
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
CE2
X
X
L
X
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
H
X
H
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
ADSP
X
L
L
H
H
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
X
ADSC
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
ADV
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
WRITE
X
X
X
X
X
X
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
X
OE
X
X
X
X
X
X
X
X
L
H
L
H
X
X
L
H
L
H
X
X
X
ISSI
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Q
D
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
High-Z
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
®
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
GW
H
H
H
H
L
BWE
H
L
L
L
X
BW1
X
H
L
L
X
BW2
X
H
H
L
X
BW3
X
H
H
L
X
BW4
X
H
H
L
X
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
05/10/01
Rev. 00A
5