WED3DG64128V-D1
1GB- 128Mx64 SDRAM, UNBUFFERED W/PLL
FEATURES
n
PC100 and PC133 compatible
n
Burst Mode Operation
n
Auto and Self Refresh capability
n
LVTTL compatible inputs and outputs
n
Serial Presence Detect with EEPROM
n
Fully synchronous: All signals are registered on the positive
edge of the system clock
n
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
n
3.3 volt
6
0.3v Power Supply
n
144 Pin SO-DIMM JEDEC
DESCRIPTION
The WED3DG64128V is a 128Mx64 synchronous DRAM module
which consists of eight 128Mx8 stack SDRAM components in
TSOP- 11 package, and one 2K EEPROM in an 8- pin TSSOP
package for Serial Presence Detect which are mounted on a 144
Pin SO-DIMM multilayer FR4 Substrate.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
A0 A12
BA0-1
DQ0-63
CLK0
CKE0, CKE1
CS0, CS1
RAS
CAS
WE
DQM0-7
VDD
VSS
SDA
SCL
DNU
NC
PIN NAMES
Address input (Multiplexed)
Select Bank
Data Input/Output
Clock input
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
Serial data I/O
Serial clock
Do not use
No Connect
NC
NC
NC
NC
CS0\
CS1\
NC
NC
NC
NC
NC
NC
White Electronic Designs Corp reserves the right to change products or specifications without notice.
June 2003 Rev. 1
ECO #16373
1
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
WED3DG64128V-D1
FUNCTIONAL BLOCK DIAGRAM
5
5
5
5
7
5
5
5
White Electronic Designs Corp reserves the right to change products or specifications without notice.
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
2
June 2003 Rev. 1
ECO #16373
WED3DG64128V-D1
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Current
Symbol
V
IN
, Vout
VDD, VDDQ
TSTG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
16
50
Units
V
V
°C
W
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(Voltage Referenced to: V
SS
= 0V, T
A
= 0°C to +70°C)
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Symbol
VDD
VIH
VIL
VOH
VOL
ILI
Min
3.0
2.0
-0.3
2.4
-10
Typ
Max
Unit
3.3
3.6
V
3.0 VDDQ+0.3 V
0.8
V
V
0.4
V
10
µA
Note
1
2
IOH= -2mA
IOL= -2mA
3
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is
£
3ns.
2. VIL (min)= -2.0V AC. The undershoot voltage duration is
£
3ns.
3. Any input 0V
£
VIN
£
VDDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State
outputs.
CAPACITANCE
(T
A
= 23°C, f = 1MHz, V
DD
= 3.3V, VREF=1.4V
6200mV)
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS,CAS,WE)
Input Capacitance (CKE0)
Input Capacitance (CLK0)
Input Capacitance (CS0)
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)
Data input/output capacitance (CB0-7)
White Electronic Designs Corp reserves the right to change products or specifications without notice.
June 2003 Rev. 1
ECO #16373
3
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
Cout
Cout 1
Min
-
-
-
-
-
-
-
-
-
Max
15
15
15
20
15
15
15
22
22
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
WED3DG64128V-D1
OPERATING CURRENT CHARACTERISTICS
(V
CC
= 3.3V, T
A
= 0°C to +70°C)
Parameter
Operating Current
(One bank active)
Precharge Standby Current
in Power Down Mode
Precharge Standby Current
in Non-Power Down Mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
Operating current (Burst mode)
Refresh current
Self refresh current
Symbol
ICC1
ICC2P
ICC2PS
Icc2N
Icc2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
ICC6
Conditions
Burst Length = 1
tRC
³
tRC(min)
IOL = 0mA
CKE
£
VIL(max), tCC = 10ns
CKE & CLK
£
VIL(max), tCC =
¥
CKE
³
VIH(min), CS
³
VIH(min), tcc = 10ns
Input signals are charged one time during 20
CKE
³
VIH(min), CLK
£
VIL(max), tcc =
¥
Input signals are stable
CKE
³
VIL(max), tCC = 10ns
CKE & CLK
£
VIL(max), tcc =
¥
CKE
³
VIH(min), CS
³
VIH(min), tcc = 10ns
Input signals are changed one time during 20ns
CKE
³
VIH(min), CLK
£
VIL(max), tcc =
¥
input signals are stable
Io = mA
Page burst
4 Banks activated
tCCD = 2CLK
tRC
³
tRC(min)
CKE
£
0.2V
Version
133
100
1,680
1,520
130
120
320
160
160
130
480
360
1,680
2,720
1,440
2,560
Units Note
mA
1
mA
mA
mA
mA
mA
mA
mA
mA
1
2
115
Notes: 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL = VDDQ/VssQ)
White Electronic Designs Corp reserves the right to change products or specifications without notice.
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
4
June 2003 Rev. 1
ECO #16373
WED3DG64128V-D1
Part number
WED3DG64128V10D1
WED3DG64128V7D1
WED3DG64128V75D1
Speed
100MHz
133MHz
133MHz
Cas Latency
CL=2
CL=2
CL=3
Note: For industrial temperature range product, add an "I" to the end of the part
number.
PACKAGE DIMENSIONS
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp reserves the right to change products or specifications without notice.
June 2003 Rev. 1
ECO #16373
5
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
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