256Kx8/128Kx16, 20 - 45ns, STACK/PGA
30A097-32
E
2 Megabit High Speed CMOS SRAM
DPS128X16Cn3/DPS128X16Bn3
DESCRIPTION:
The DPS128X16Cn3/DPS128X16Bn3 High Speed SRAM ‘’STACK’’
modules are a revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages, or
mounted on a 50-pin PGA co-fired ceramic substrate. The module
packs 2-Megabits of low-power CMOS static RAM in an area as small
as 0.463 in
2
, while maintaining a total height as low as 0.171 inches.
The DPS128X16Cn3/DPS128X16Bn3 STACK modules contain two
individual 128K x 8 SRAMs, each packaged in a hermetically sealed
SLCC, making the modules suitable for commercial, industrial and
military applications.
The DPS128X16Bn3 has one active low Chip Enable (CE) and while the
DPS128X16Cn3 an active low Chip Enable (CE) and an active high
Select Line (SEL).
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC Stack
Straight Leaded
Stack
FEATURES:
•
•
•
•
•
•
•
•
Organizations Available: 128Kx16 or 256Kx8
Access Times: 20, 25, 30, 35, 45ns
Fully Static Operation - No clock or refresh required
Single +5V Power Supply,
±
10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage: 2.0V min.
Packages Available:
48 - Pin SLCC Stack
48 - Pin Straight Leaded Stack
48 - Pin ‘’J’’ Leaded Stack
48 - Pin Gullwing Leaded Stack
50 - Pin PGA Dense-Stack
‘’J’’ Leaded
Stack
Dense-Stack
Gullwing
Leaded Stack
30A097-32
REV. G
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS128X16Cn3/DPS128X16Bn3
Dense-Pac Microsystems, Inc.
FUNCTIONAL BLOCK DIAGRAM
PIN NAMES
A0 - A16
Address Inputs
I/O0 - I/O15
Data Input/Output
CE0, CE1
Low Chip Enables
SEL0, SEL1
High Chip Enables
WE
Write Enable
OE
Output Enable
V
DD
Power (+5V)
V
SS
Ground
N.C.
No Connect
NOTE:
SEL0 and SEL1 apply to DPS128X16Cn3 version only.
PIN-OUT DIAGRAM
48 - PIN LEADLESS STACK
48 - PIN STRAIGHT LEADED STACK
48 - PIN ‘’J’’ LEADED STACK
48 - PIN GULLWING LEADED STACK
50 - PIN PGA
DENSE-STACK
NOTE:
SEL0 and SEL1 apply to DPS128X16Cn3 version only, No Connect for DPS128X16Bn3 version.
2
30A097-32
REV. G
Dense-Pac Microsystems, Inc.
DPS128X16Cn3/DPS128X16Bn3
RECOMMENDED OPERATING RANGE
3
TRUTH TABLE
Mode
Not Selected
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
Symbol
Characteristic
Min. Typ.
Max. Unit
V
DD
Supply Voltage
4.5 5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.5
2
0.8
V
M/B -55 +25 +125
Operating
o
T
A
I
-40 +25
+85
C
Temperature
C
0 +25
+70
SEL
L
X
H
H
H
CE
X
H
L
L
L
WE
X
X
H
H
L
OE
X
X
H
L
X
Supply
I/O Pin Current
High-Z Standby
High-Z Standby
High-Z Active
D
OUT
Active
D
IN
Active
X = Don’t Care
NOTE:
SEL applies to DPS128X16Cn3 version only.
L = LOW
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4.0mA 2.4
V
I
OL
=8.0mA
0.4
V
CAPACITANCE
4
:
T
A
= 25°C, F = 1.0MHz
Symbol
Parameter
C
ADR
Address Input
C
CE
Chip Enable
Active High
C
SEL
Chip Select
C
WE
Write Enable
C
OE
Output Enable
C
I/O
Data Input/Output
Max.
25
25
25
30
25
20
Unit
Condition
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STC
T
BIAS
V
DD
V
I/O
Parameter
Storage Temperature
Temperature Under Bias
Supply Voltage
1
Input/Output Voltage
1
3
Value
Unit
-65 to +150
°C
-55 to +125
°C
-0.5 to +7.0
°C
-0.5 to V
DD
+0.5 V
pF
V
IN2
= 0V
NOTE:
C
SEL
applies to DPS128X16Cn3 version only.
DC OPERATING CHARACTERISTICS:
Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current (TTL)
Data Retention
Supply Current
(3.0V)
Data Retention
Supply Current
(2.0V)
Output Low Voltage
Output High Voltage
o
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
Cycle=min., Duty=100%
I
OUT
= 0mA
X8
X16
Typ.
(†)
-
-
125
200
0.8
50
140
70
-
-
C
Min.
Max.
Min.
I
Max.
Min.
M
Max.
Unit
µA
µA
mA
mA
mA
µA
µA
V
V
-10
-10
+10
+10
180
280
10
80
800
500
0.4
-10
-10
+10
+10
190
280
10
100
1200
800
0.4
-10
-10
+10
+10
210
320
20
100
4600
3600
0.4
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
V
DR
= 3.0V, CE
≥
V
DR
-0.2V,
(or SEL
≤
0.2V, V
IN
≥
V
DD
-0.2V
or V
IN
≤
+0.2V)
V
DR
= 2.0V, CE
≥
V
DR
-0.2V,
(or SEL
≤
0.2V, V
IN
≥
V
DD
-0.2V
or V
IN
≤
+0.2V)
I
OUT
= 8.0mA
I
OUT
= -4.0mA
2.4
2.4
2.4
† Typical measurements made at +25 C, Cycle = min., V
DD
= 5.0V.
NOTE:
Test Conditions in parenthesis apply to DPS128X16Cn3 version only.
30A097-32
REV. G
3
DPS128X16Cn3/DPS128X16Bn3
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns
1.5V
Dense-Pac Microsystems, Inc.
Figure 1.
Output Load
* Including Probe and Jig Capacitance.
+5V
480Ω
OUTPUT LOAD
Load
1
2
C
L
100pF
5pF
Parameters Measured
except t
LZ1
, t
LZ2
, t
HZ1
, t
HZ2
, t
OHZ
, t
OLZ
,
and t
WHZ
t
LZ1
, t
LZ2
, t
HZ1
, t
HZ2
, t
OHZ
, t
OLZ
, and t
WHZ
D
OUT
C
L
*
255Ω
NOTE:
t
LZ2
and t
HZ2
apply to DPS128X16Cn3 version only.
Data Retention AC Characteristics
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data
Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V, (SEL
≥
V
DR
-0.2V,
or V
IN
≤
V
DR
-0.2V or V
IN
≤
0.2V)
See Data Retention Waveform
See Data Retention Waveform
8
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
NOTE:
Test Conditions in parenthesis apply to DPS128X16Cn3 version only.
DATA RETENTION WAVEFORM:
V
DD
4.5V
2.3V
V
DR1
CE
0V
CE
≥
V
DD
-0.2V
CE Controlled.
DATA RETENTION WAVEFORM:
V
DD
4.5V
SEL
V
DR2
0.4V
0V
SEL Controlled. (Applies to DPS128X16Cn3 only)
SEL
≤
-0.2V
4
30A097-32
REV. G
Dense-Pac Microsystems, Inc.
DPS128X16Cn3/DPS128X16Bn3
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
No. Symbol
1
2
3
4
5
6
7
8
9
10
11
12
t
RC
t
AA
t
CO1
t
CO2
t
OE
t
LZ1
t
LZ2
t
OLZ
t
HZ1
t
HZ2
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Access Time
CE to Output Valid
SEL to Output Valid
Output Enable to Output Valid
CE to Output in LOW-Z
4, 5
SEL to Output in LOW-Z
4, 5
Output Enable to Output in LOW-Z
4, 5
CE to Output in HIGH-Z
4, 5
SEL to Output in HIGH-Z
4, 5
Output Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
20ns
Min.
Max.
Over operating ranges
35ns
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
20
8
3
3
0
10
10
8
3
25
25
25
25
10
3
3
0
12
12
10
3
30
30
30
30
15
3
3
0
15
15
15
3
35
35
35
35
20
3
3
0
20
20
20
3
45
45
45
45
25
3
3
0
25
25
25
3
NOTE:
t
CO2
, t
LZ2
and t
HZ2
apply to DPS128X16Cn3 version only.
READ CYCLE
ADDRESS
CE
SEL
OE
DATA I/O
NOTE:
SEL, t
CO2
, t
LZ2
and t
HZ2
apply to DPS128X16Cn3 version only.
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
30A097-32
REV. G
5
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