Integrated
Circuit
Systems, Inc.
ICS9248-96
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset.
Output Features:
•
2- CPUs @ 2.5V, up to 166.5MHz.
•
9 - SDRAM @ 3.3V, up to 155MHz including
1 free running
•
8 - PCICLK @ 3.3V
•
1 - IOAPIC @ 2.5V,
•
2 - 3V66MHz @ 3.3V, 2X PCI MHz
•
2 - 48MHz, @ 3.3V fixed.
•
1 - 24/48MHz, @3.3V selectable by I
2
C
•
1 - REF @v3.3V, 14.318MHz.
Features:
•
Up to 166.5MHz frequency support
•
Support FS0-FS3 strapping status bit for I
2
C read
back.
•
Support power management: Through Power down
Mode from I
2
C programming.
•
Spread spectrum for EMI control ( ± 0.25% center).
•
Uses external 14.318MHz crystal
Skew Specifications:
•
CPU – CPU: <175ps
•
SDRAM - SDRAM: < 250ps
•
3V66 – 3V66: <175ps
•
PCI – PCI: <500ps
•
CPU-SDRAM<500ps
•
For group skew specifications, please refer to group
timing relationship table.
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
** 60K pull-up to VDD on indicated input
1 These are double strength.
Block Diagram
Functionality
FS3
FS2
FS1
FS0
CPU
(MHz)
SDRAM
(MHz)
3V66
(MHz)
PCICLK
(MHz)
I OA P I C
1=PCICLK/2
I OA P I C
0=PCICLK
(MHz)
(MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.80
68.00
100.30
103.00
133.73
145.00
133.73
137.33
140.00
140.00
118.00
124.00
133.70
137.00
150.00
72.50
100.20
102.00
100.30
103.00
100.30
108.75
100.30
103.00
105.00
140.00
118.00
124.00
133.70
137.00
112.50
108.75
66.80
68.00
66.87
68.67
66.87
72.50
66.87
68.67
70.00
93.33
78.67
82.67
89.13
91.33
75.00
72.50
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
16.70
17.00
16.72
17.17
16.72
18.13
16.72
17.17
17.50
23.33
19.67
20.67
22.28
22.83
18.75
18.13
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
Additional frequencies
programming.
selectable
through
I
2
C
0311D—04/23/04
ICS9248-96
General Description
ICS9248-96
is the single chip clock solution for designs
using the 810/810E style chipset. It provides all necessary
clock signals for such a system.
Spread spectrum may be enabled through I
2
C
programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting
to board design iterations or costly shielding. The ICS9248-
96 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection.
Power Groups
GNDREF, VDDREF = REF0, X1, X2
GNDPCI , VDDPCI = PCICLK [9:0]
GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F,
supply for PLL core
GND3V66 , VDD3V66 = 3V66
GND48 , VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU , VDDLCPU = CPUCLK [1:0]
Pin Configuration
PIN NUMBER
1
2, 9, 10, 18, 25,
30, 38
3
4
5, 6, 14, 21, 29,
34, 42
8, 7
11
12
PIN NAME
FREQ_IOAPIC
REF0
VDD
X1
X2
GND
3V66 [1:0]
FS0
PCICLK0
FS1
PCICLK1
SEL24_48MHz#
PCICLK2
PCICLK [7:3]
PD#
SCLK
SDATA
FS3
48MHz_0
48MHz_1
TYPE
IN
OUT
PWR
IN
OUT
PWR
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
DESCRIPTION
If FREQ_APIC = 0, APIC Clock = PCICLK
If FREQ_APIC = 1, APIC Clock = PCICLK/2 (default)
14.318 MHz reference clock.
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Ground pin for 3V outputs.
3.3V Clocks
Frequency select pin.
PCI clock output
Frequency select pin.
PCI clock output
Logic inputs frequency select I/O/USB output,
When a "0" is latched, output frequency = 48MHz
When a "1" is latched, output frequency = 24MHz
PCI clock output
PCI clock outputs.
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms.
Clock input of I2C input, 5V tolerant input
Data input for I2C serial input, 5V tolerant input
Frequency select pin.
48MHz output clocks
48MHz output clocks
Frequency select pin.
13
20, 19, 17, 16, 15
22
23
24
26
27
28
31
FS2
24_48MHz
SDRAM_F
OUT
OUT
OUT
PWR
OUT
PWR
OUT
PWR
24 or 48MHz output
Free running SDRAM - used for feed back to chipset, should remain
on always.
SDRAM clock outputs
Ground pin for the CPU clocks.
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
2.5V clock output
Power pin for the IOAPIC. 2.5V
32, 33, 35, 36, 37,
SDRAM [7:0]
39, 40, 41,
43
GNDLCPU
44, 45
CPUCLK [1:0]
46
VDDLCPU
47
IOAPIC
48
0311D—04/23/04
VDDLAPIC
2
ICS9248-96
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will
acknowledge
each byte
one at a time.
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Dummy Byte Count
ACK
Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Stop Bit
ACK
Stop Bit
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0311D—04/23/04
3
ICS9248-96
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit (2, 7:4)
CPUCLK
(MHz)
SDRAM
(MHz)
Description
3V66
(MHz)
PCICLK
(MHz)
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
37.50
13.83
36.67
40.00
41.67
34.63
35.00
38.33
48.33
33.25
50.00
33.25
51.67
55.50
38.33
33.25
FREQ_IOAPIC
(MHz)
1
0
16.70
33.40
17.00
34.00
16.72
33.43
17.17
34.33
16.72
33.43
18.13
36.25
16.72
33.43
17.17
34.33
17.50
35.00
23.33
46.67
19.67
39.33
20.67
41.33
22.28
44.57
22.83
45.67
18.75
37.50
18.13
36.25
18.75
37.50
6.92
13.83
18.33
36.67
20.00
40.00
20.83
41.67
17.31
34.63
17.50
35.00
19.17
38.33
24.17
48.33
16.63
33.25
25.00
50.00
16.63
33.25
25.83
51.67
27.75
55.50
19.17
38.33
16.63
33.25
Spread Precentage
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center*
+/- 0.25% Center*
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center*
PWD
0
0
0
0
0
66.80
100.20
66.80
0
0
0
0
1
68.00
102.00
68.00
0
0
0
1
0
100.30
100.30
66.87
0
0
0
1
1
103.00
103.00
68.67
0
0
1
0
0
133.73
100.30
66.87
0
0
1
0
1
145.00
108.75
72.50
0
0
1
1
0
133.73
100.30
66.87
0
0
1
1
1
137.33
103.00
68.67
0
1
0
0
0
140.00
105.00
70.00
0
1
0
0
1
140.00
140.00
93.33
0
1
0
1
0
118.00
118.00
78.67
124.00
124.00
82.67
0
1
0
1
1
0
1
1
0
0
133.70
133.70
89.13
0
1
1
0
1
137.00
137.00
91.33
Bit 2,
150.00
112.50
75.00
0
1
1
1
0
Bit 7:4
0
1
1
1
1
72.50
108.75
72.50
1
0
0
0
0
75.00
112.50
75.00
1
0
0
0
1
83.00
83.00
27.67
1
0
0
1
0
110.00
110.00
73.33
120.00
120.00
80.00
1
0
0
1
1
1
0
1
0
0
125.00
125.00
83.33
1
0
1
0
1
69.25
103.88
69.25
1
0
1
1
0
70.00
105.00
70.00
1
0
1
1
1
76.67
115.00
76.67
1
1
0
0
0
145.00
145.00
96.67
1
1
0
0
1
66.50
99.75
66.50
1
1
0
1
0
150.00
150.00
100.00
1
1
0
1
1
99.75
99.75
66.50
1
1
1
0
0
155.00
155.00
103.33
166.50
166.50
111.00
1
1
1
0
1
1
1
1
1
0
153.33
115.00
76.67
1
1
1
1
1
133.00
99.75
66.50
0 - Frequency is selected by hardware select, Latched Inputs
Bit 3
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
Bit 1
1 - Spread Spectrum Enabled ± 0.25% Center Spread
0 - Running
Bit 0
1- Tristate all outputs
00011
Note1
0
1
0
Note 1:
Default at power-up will be for latched logic inputs to define frequency (Bit 3 = 0).
* These frequencies with spread enabled are equal to original Intel defined frequencies with -0.5% down spread.
I
2
C is a trademark of Philips Corporation
0311D—04/23/04
4
ICS9248-96
Byte 1: Control Register
(1= enable, 0 = disable)
Byte 2: SDRAM, Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
28
27
26
-
31
PWD
X
X
X
X
1
1
1
1
DESCRIPTION
FS3#
FS0#
FS2#
24_48MHz, 0 = 24MHz
48MHz_1
48MHz_0
( R e s e r ve d )
SDRAM_F
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
32
33
35
36
37
39
40
41
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 3: PCI, Control Register
(1= enable, 0 = disable)
Byte 4: Control Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
20
19
17
16
15
13
12
11
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
8
7
-
47
-
44
45
PWD
1
1
1
X
1
X
1
1
DESCRIPTION
( R e s e r ve d )
3V66_1
3V66_0
FREQ_IOAPIC#
IOAPIC
FS1#
CPUCLK1
CPUCLK0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Notes:
PIN#
-
-
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
R e s e r ve d
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN#
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
1
1
0
DESCRIPTION
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
1. Disable means outputs are held LOW and are
disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted
logic load of the input frequency select pin conditions.
Note: Don’t write into this register. Writing into this
register can cause malfunction
0311D—04/23/04
5
京公网安备 11010802033920号
EEWORLD
