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DPS128X16CY3-35B

Description
SRAM Module, 128KX16, 35ns, CMOS, CQCC48, LEADLESS, STACK, SLCC-48
Categorystorage    storage   
File Size577KB,10 Pages
ManufacturerTwilight Technology Inc.
Download Datasheet Parametric View All

DPS128X16CY3-35B Overview

SRAM Module, 128KX16, 35ns, CMOS, CQCC48, LEADLESS, STACK, SLCC-48

DPS128X16CY3-35B Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeLCC
package instructionAQCCN, LCC48,.5X.87
Contacts48
Reach Compliance Codeunknow
ECCN code3A001.A.2.C
Maximum access time35 ns
Other featuresCONFIGURABLE AS 128K X 16
Spare memory width8
I/O typeCOMMON
JESD-30 codeR-CQCC-N48
length22.098 mm
memory density2097152 bi
Memory IC TypeSRAM MODULE
memory width16
Number of functions1
Number of terminals48
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX16
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeAQCCN
Encapsulate equivalent codeLCC48,.5X.87
Package shapeRECTANGULAR
Package formCHIP CARRIER, PIGGYBACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Filter level38535Q/M;38534H;883B
Maximum seat height4.3434 mm
Maximum standby current0.0036 A
Minimum standby current2 V
Maximum slew rate0.32 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width12.7 mm
Base Number Matches1
256Kx8/128Kx16, 20 - 45ns, STACK/PGA
30A097-32
E
2 Megabit High Speed CMOS SRAM
DPS128X16Cn3/DPS128X16Bn3
DESCRIPTION:
The DPS128X16Cn3/DPS128X16Bn3 High Speed SRAM ‘’STACK’’
modules are a revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages, or
mounted on a 50-pin PGA co-fired ceramic substrate. The module
packs 2-Megabits of low-power CMOS static RAM in an area as small
as 0.463 in
2
, while maintaining a total height as low as 0.171 inches.
The DPS128X16Cn3/DPS128X16Bn3 STACK modules contain two
individual 128K x 8 SRAMs, each packaged in a hermetically sealed
SLCC, making the modules suitable for commercial, industrial and
military applications.
The DPS128X16Bn3 has one active low Chip Enable (CE) and while the
DPS128X16Cn3 an active low Chip Enable (CE) and an active high
Select Line (SEL).
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC Stack
Straight Leaded
Stack
FEATURES:
Organizations Available: 128Kx16 or 256Kx8
Access Times: 20, 25, 30, 35, 45ns
Fully Static Operation - No clock or refresh required
Single +5V Power Supply,
±
10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Voltage: 2.0V min.
Packages Available:
48 - Pin SLCC Stack
48 - Pin Straight Leaded Stack
48 - Pin ‘’J’’ Leaded Stack
48 - Pin Gullwing Leaded Stack
50 - Pin PGA Dense-Stack
‘’J’’ Leaded
Stack
Dense-Stack
Gullwing
Leaded Stack
30A097-32
REV. G
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
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