CS49300
Multi-Standard Audio Decoder Family
Features
l
CS4930X: DVD Audio Sub-family
— PES layer decode for A/V sync
— DVD Audio Pack Layer Support
— Meridian Lossless Packing (MLP)™
— Dolby Digital™
— MPEG Multi-Channel
— DTS Digital Surround™
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CS4931X: Broadcast Sub-family
— PES layer decode for A/V sync
— MPEG Advanced Audio Coding Algorithm (AAC)
— MPEG Multi Channel
— Dolby Digital
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CS4932X: AVR Sub-family
— Dolby Digital with integrated code
— DTS decoding with integrated DTS tables & code
— Crystal Original Surround with integrated code
— MPEG Advanced Audio Coding Algorithm (AAC)
— MPEG Multi-Channel
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CS4933X: General Purpose Audio DSP
— THX™ and THX Surround EX
— Car Audio
— Mixer Applications
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Features are a super-set of the CS4923/4/5/6/7/8
— 8 channel output, including dual zone output
capability
— Supports up to 192 kHz Fs @ 24 bit throughput
— Increased memory/MIPs
— SRAM Interface for increased delay and buffer
capability
— MPEG Layer 3 (MP3)
Description
The CS493XX is a family of multichannel audio decoders
intended to supersede the CS4923/4/5/6/7/8 family as the
leader of audio decoding in both the DVD, broadcast and
receiver markets. The family will be split into parts tailored
for each of these distinct market segments.
For the DVD market, parts will be offered which support
Meridian Lossless Packing (MLP), Dolby Digital, MPEG
Multi-Channel, DTS and subsets thereof. For the receiver
market, parts will be offered which support Dolby Digital,
MPEG Multi-Channel, DTS, AAC and subsets thereof.
For the broadcast market parts will be offered which
support Dolby Digital, MPEG Advanced Audio Coding
(AAC), and MPEG Multi-Channel.
Under the Crystal brand, Cirrus Logic is the only single
supplier of high-performance 24-bit multi-standard audio
DSP decoders, DSP firmware, and high-resolution data
converters. This combination of DSPs, system firmware,
and data converters simplify rapid creation of world-class
high-fidelity products.
Ordering Information:
See page 68
APPLICATION
CS49300
CS49310
CS49325
CS49326
CS49329
CS49330
DVD Audio
Broadcast
AVR
AVR
AVR
Audio DSP
FEATURES
MLP, AC3, DTS and MPEG5.1
AAC, AC3, MPEG5.1
AC3(IBA), MPEG5.1
AC3(IBA), DTS(IBA), MPEG5.1
AC3(IBA), AAC, DTS, MPEG5.1,
PCM Pass-through (IBA)
THX
RESET
CMPDAT,
SDATAN2
CMPCLK,
SCLKN2
CMPREQ,
LRCLKN2
SCLKN1,
STCCLK2
LRCLKN1
SDATAN1
CLKIN
CLKSEL
RD,
WR,
SCDIO,
DATA7:0,
R/W,
DS,
SCDOUT,
EMOE, EMWR,
PSEL,
ABOOT,
EMAD7:0,
A0,
A1,
GPIO7:0
CS
GPIO11 GPIO10 GPIO9 SCCLK SCDIN
INTREQ
EXTMEM,
GPIO8
DD
DC
Compressed
Data Input
Interface
Parallel or Serial Host Interface
Framer
Shifter
Input
Buffer
Controller
24-Bit
DSP Processing
RAM
RAM
Program Data
Memory Memory
ROM
ROM
Program Data
Memory Memory
STC
MCLK
SCLK
Output
Formatter
LRCLK
AUDATA[2.0]
Digital
Audio
Input
Interface
PLL
Clock Manager
FILT2 FILT1
RAM Input
Buffer
RAM
Output
Buffer
XMT958/AUDATA3
VA AGND
DGND[3:1]
VD[3:1]
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
©
Cirrus Logic, Inc. 1999
(All Rights Reserved)
NOV ‘99
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CS49300
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ................................................................ 6
ABSOLUTE MAXIMUM RATINGS..................................................................................... 6
RECOMMENDED OPERATING CONDITIONS................................................................. 6
DIGITAL D.C. CHARACTERISTICS .................................................................................. 6
POWER SUPPLY CHARACTERISTICS............................................................................ 6
SWITCHING CHARACTERISTICS — RESET .................................................................. 7
SWITCHING CHARACTERISTICS—CLKIN...................................................................... 7
SWITCHING CHARACTERISTICS—INTEL
®
HOST MODE ............................................. 8
SWITCHING CHARACTERISTICS—MOTOROLA
®
HOST MODE................................. 10
SWITCHING CHARACTERISTICS—DIGITAL AUDIO INPUT ........................................ 16
SWITCHING CHARACTERISTICS—CMPDAT, CMPCLK .............................................. 17
SWITCHING CHARACTERISTICS—PARALLEL DATA INPUT...................................... 17
SWITCHING CHARACTERISTICS—DIGITAL AUDIO OUTPUT .................................... 18
2. FAMILY OVERVIEW ....................................................................................................... 20
2.1 Multi-channel Decoder Family of Parts ..................................................................... 20
3. TYPICAL CONNECTION DIAGRAMS ........................................................................... 21
3.1 Multiplexed Pins ........................................................................................................ 21
3.2 Termination Requirements ........................................................................................ 22
3.3 Phase Locked Loop Filter ......................................................................................... 22
4. POWER ........................................................................................................................... 29
4.1 Decoupling ................................................................................................................ 29
4.2 Analog Power Conditioning ....................................................................................... 29
4.3 Ground ...................................................................................................................... 29
4.4 Pads .......................................................................................................................... 29
5. CLOCKING ..................................................................................................................... 29
6. CONTROL ....................................................................................................................... 30
6.1 Serial Communication ............................................................................................... 30
6.1.1 SPI Communication ...................................................................................... 30
6.1.1.1 Writing in SPI ...................................................................................... 30
6.1.1.2 Reading in SPI .................................................................................... 31
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Dolby and Dolby Pro Logic are registered trademarks, Dolby Digital is a trademark of Dolby Laboratories Licensing Corporation.
Intel is a registered trademark of Intel Corporation.
Motorola is a registered trademark of Motorola, Inc.
I
2
C is a registered trademark of Philips Semiconductor.
THX is a registered trademark of LucasArts Entertainment Company.
All other names are trademarks, registered trademarks, or service marks of their respective companies.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
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CS49300
6.1.2 I
2
C Communication ...................................................................................... 32
6.1.2.1 Writing in I
2
C ....................................................................................... 34
6.1.2.2 Reading in I
2
C ..................................................................................... 34
6.1.3 INTREQ Behavior: A Special Case .............................................................. 36
6.2 Parallel Host Communication ................................................................................... 39
6.2.1 Intel Parallel Host Communication Mode ..................................................... 39
6.2.1.1 Writing a Byte in Intel Mode ................................................................ 41
6.2.1.2 Reading a Byte in Intel Mode .............................................................. 41
6.2.2 Motorola Parallel Host Communication Mode .............................................. 42
6.2.2.1 Writing a Byte in Motorola Mode ......................................................... 42
6.2.2.2 Reading a Byte in Motorola Mode ....................................................... 43
6.2.3 Procedures for Parallel Host Mode Communication .................................... 43
6.2.3.1 Control Write in a Parallel Host Mode ................................................. 43
6.2.3.2 Control Read in a Parallel Host Mode ................................................. 44
7. EXTERNAL MEMORY .................................................................................................... 46
7.1 Memory Paging ....................................................................................................... 46
8. BOOT PROCEDURE & RESET ..................................................................................... 48
8.1 Host Boot .................................................................................................................. 48
8.2 Autoboot ................................................................................................................... 50
8.2.1 Autoboot INTREQ Behavior ......................................................................... 51
8.3 Internal Boot ............................................................................................................. 53
8.4 Application Failure Boot Message ............................................................................ 53
8.5 Resetting the CS493XX ............................................................................................ 53
9. DIGITAL INPUT & OUTPUT ........................................................................................... 54
9.1 Digital Audio Formats ............................................................................................... 54
9.1.1 I
2
S ................................................................................................................ 54
9.1.2 Left Justified ................................................................................................. 54
9.1.3 Multi-Channel ............................................................................................... 55
9.2 Digital Audio Input Port ............................................................................................. 55
9.3 Compressed Data Input Port .................................................................................... 56
9.4 Byte Wide Digital Audio Data Input .......................................................................... 56
9.4.1 Parallel Delivery with Parallel Control .......................................................... 56
9.4.2 Parallel delivery with serial control ............................................................... 57
9.5 Digital Audio Output Port .......................................................................................... 57
9.5.1 IEC60958 Output .......................................................................................... 58
10.HARDWARE CONFIGURATION ................................................................................... 59
10.1 Address Checking ................................................................................................... 59
10.2 Input ....................................................................................................................... 59
10.2.1 Input Configuration Considerations ........................................................... 61
10.3 Output ..................................................................................................................... 61
10.3.1 Output Configuration Considerations ........................................................ 61
10.4 Creating Hardware Configuration Messages .......................................................... 63
11.PIN DESCRIPTIONS ...................................................................................................... 64
12.ORDERING INFORMATION .......................................................................................... 68
13.PACKAGE DIMENSIONS .............................................................................................. 69
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CS49300
LIST OF FIGURES
Figure 1. RESET Timing ................................................................................................................. 7
Figure 2. CLKIN with CLKSEL = VSS = PLL Enable ...................................................................... 7
Figure 3. CLKIN with CLKSEL = VD = PLL Bypass ........................................................................ 7
Figure 4. Intel
®
Parallel Host Mode Read Cycle ............................................................................. 9
Figure 5. Intel
®
Parallel Host Mode Write Cycle ............................................................................. 9
Figure 6. Motorola
®
Parallel Host Mode Read Cycle .................................................................... 11
Figure 7. Motorola
®
Parallel Host Mode Write Cycle .................................................................... 11
Figure 8. Digital Audio Input Data, Master and Slave Clock Timing.............................................. 16
Figure 9. Serial Compressed Data Timing .................................................................................... 17
Figure 10. Parallel Data Timing (when not in a parallel control mode).......................................... 17
Figure 11. Digital Audio Output Data, Input and Output Clock Timing .......................................... 19
Figure 12. I
2
C
®
Control ................................................................................................................. 23
Figure 13. I
2
C
®
Control with External Memory.............................................................................. 24
Figure 14. SPI
®
Control................................................................................................................. 25
Figure 15. SPI
®
Control with External Memory ............................................................................. 26
Figure 16. Intel
®
Parallel Control Mode......................................................................................... 27
Figure 17. Motorola
®
Parallel Control Mode ................................................................................. 28
Figure 18. SPI Write Flow Diagram............................................................................................... 31
Figure 19. SPI Read Flow Diagram............................................................................................... 31
Figure 20. SPI Timing.................................................................................................................... 33
Figure 21. I
2
C Write Flow Diagram ............................................................................................... 34
Figure 22. I
2
C Read Flow Diagram ............................................................................................... 35
Figure 23. I
2
C Timing .................................................................................................................... 37
Figure 24. Intel Mode, One-Byte Write Flow Diagram................................................................... 41
Figure 25. Intel Mode, One-Byte Read Flow Diagram .................................................................. 42
Figure 26. Motorola Mode, One-Byte Write Flow Diagram ........................................................... 43
Figure 27. Motorola Mode, One-Byte Read Flow Diagram ........................................................... 43
Figure 28. Typical Parallel Host Mode Control Write Sequence Flow Diagram ............................ 44
Figure 29. Typical Parallel Host Mode Control Read Sequence Flow Diagram............................ 45
Figure 30. External Memory Interface ........................................................................................... 47
Figure 31. External Memory Read (16 bit address) ..................................................................... 47
Figure 32. External Memory Write (16 bit address)....................................................................... 47
Figure 33. Typical Serial Boot and Download Procedure.............................................................. 49
Figure 34. Autoboot Timing Diagram ............................................................................................ 50
Figure 35. Autoboot Sequence...................................................................................................... 52
Figure 36. Autoboot INTREQ Behavior ......................................................................................... 53
Figure 37. Performing a Reset ...................................................................................................... 54
Figure 38. I
2
S
®
Format.................................................................................................................. 55
Figure 39. Left Justified Format (Rising Edge Valid SCLK) .......................................................... 55
Figure 40. Multi-Channel Format................................................................................................... 55
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DS339PP1
CS49300
LIST OF TABLES
Table 1. PLL Filter Component Values ......................................................................................... 22
Table 2. Host Modes ..................................................................................................................... 30
Table 3. SPI Communication Signals............................................................................................ 30
Table 4. I
2
C Communication Signals ........................................................................................... 32
Table 5. Parallel Input/Output Registers ....................................................................................... 40
Table 6. Intel Mode Communication Signals................................................................................. 41
Table 7. Motorola Mode Communication Signals ......................................................................... 42
Table 8. Memory Interface Pins .................................................................................................... 46
Table 9. Boot Write Messages ...................................................................................................... 48
Table 10. Boot Read Messages.................................................................................................... 48
Table 11. Digital Audio Input Port ................................................................................................. 55
Table 12. Compressed Data Input Port......................................................................................... 56
Table 13. Digital Audio Output Port............................................................................................... 57
Table 14. MCLK/SCLK Master Mode Ratios................................................................................. 58
Table 15. Output Channel Mapping .............................................................................................. 58
Table 16. Input Data Type Configuration ...................................................................................... 60
Table 17. Input Data Format Configuration................................................................................... 60
Table 18. Input SCLK Polarity Configuration ................................................................................ 61
Table 19. FIFO Setup Configuration ............................................................................................. 61
Table 20. Output Clock Configuration ........................................................................................... 61
Table 21. Output Data Format Configuration ................................................................................ 62
Table 22. Output MCLK Configuration .......................................................................................... 62
Table 23. Output SCLK Configuration........................................................................................... 62
Table 24. Output SCLK Polarity Configuration.............................................................................. 62
Table 25. Example Values to be Sent to CS493XX After Download or Soft Reset ...................... 63
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