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PDM31048LL70TTY

Description
Standard SRAM, 256KX8, 70ns, CMOS, PDSO32
Categorystorage    storage   
File Size281KB,8 Pages
ManufacturerParadigm Technology Inc
Download Datasheet Parametric View All

PDM31048LL70TTY Overview

Standard SRAM, 256KX8, 70ns, CMOS, PDSO32

PDM31048LL70TTY Parametric

Parameter NameAttribute value
MakerParadigm Technology Inc
package instruction,
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time70 ns
JESD-30 codeR-PDSO-G32
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX8
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal locationDUAL
PRELIMINARY
PDM31048LL
256K x 8-Bit Low Power
3.3 Volt
Features
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Description
The PDM31048LL is a very low power CMOS static
RAM organized as 131,072 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE1) inputs are both LOW, and
CE2 is high. Reading is accomplished when WE and
CE2 remain HIGH and CE1 and OE are both LOW.
The PDM31048LL operates from a single +3.3V
power supply and all the inputs and outputs are
fully TTL- compatible. The device supports low data
retention voltage for battery back-up operation with
low current.
The PDM31048LL is available in a 32-pin plastic
TSOP (I) and a 32-pin plastic STSOP (I).
High-speed access times
Com’l: 70, 85 and 100ns
Low power operation (typical)
- PDM31048LL
Active: 65 mW
Standby: 7µW
Single +3.3V (±0.3V) power supply
TTL-compatible inputs and outputs
I/Os are 5V tolerant
Low data retention voltage: 1.5V
Packages
Plastic TSOP (I) - T
Plastic STSOP (I) - ST
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Functional Block Diagram
Addresses
A
0
A
17
Decoder
Memory
Matrix
I/O
0
I/O
7
• • • • •
Input
Data
Control
Column I/O
CE1
CE2
WE
OE
Control
Rev. 0.0 - 4/03/98
1
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