EEWORLDEEWORLDEEWORLD

Part Number

Search

530HA671M000DG

Description
CMOS/TTL Output Clock Oscillator, 671MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530HA671M000DG Overview

CMOS/TTL Output Clock Oscillator, 671MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530HA671M000DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency671 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
PYB Nano Development Board Quick Guide
[i=s]This post was last edited by dcexpert on 2016-10-31 12:14[/i] [b][size=5]PYB Nano Development Board Quick Guide[/size][/b] This quick guide is written for beginners of MicroPython and PYB Nano. T...
dcexpert Robotics Development
Is there anyone who has succeeded in UDP communication under WinCE?
I use a WinCE terminal to communicate with UDP and send data to a server, but the server cannot receive the data. However, if I use the WinCE terminal as a server, it can receive the data. I don't kno...
bathers Embedded System
About PCB Copper Covering
I have a question. When copper pouring on PCB, I set a prohibited copper pouring area polygon pour cutout. In the end, I did not remove the dotted box in the polygon pour cutout area before making the...
皇极F1 Analog electronics
Please help me with the speed of running convolutional neural network on Altera DE1-SOC
I want to use the Altera DE1-SOC development board to make a simple convolutional neural network [color=rgb(0, 0, 0)][backcolor=rgb(228, 240, 253)], such as cifar10. I only perform classification on t...
zxy7895123 FPGA/CPLD
430 MCU and Ultrasonic Sensor
Which pins should be connected to connect the 430 microcontroller to the ultrasonic sensor?...
鸽子情缘大连 Microcontroller MCU
Ask a question about wince webserver control hardware?
I have seen the QQ2440 board, in which Linux uses CGI to control the LED running lights. I don't know if WinCE uses webserve to control the LED running lights....
bbslb Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2244  1409  1278  648  2721  46  29  26  14  55 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号