= 2.7 V to 5.5 V, AGND = DGND = 0 V. All specifications T
MIN
to T
MAX
,
unless otherwise noted.)
Test Conditions/
Comments
B Version
J Version S Version Unit
DYNAMIC PERFORMANCE
2
Signal-to-(Noise + Distortion) Ratio
3
@ 25°C
70
T
MIN
to T
MAX
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise
3
Intermodulation Distortion (IMD)
3
Second Order Terms
Third Order Terms
DC ACCURACY
Resolution
Minimum Resolution for Which No
Missing Codes Are Guaranteed
Relative Accuracy
3
Differential Nonlinearity
3
Positive Full-Scale Error
3
Unipolar Offset Error
ANALOG INPUT
Input Voltage Range
Input Current
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Output Coding
CONVERSION RATE
Conversion Time
Mode 1 Operation
Mode 2 Operation
5
Track-and-Hold Acquisition Time
3
–
77
–80
12
12
±
1
±
1
±
3
±
4
±
4
0 to +V
DD
±
2
2.0
2.4
0.8
±
10
10
2.4
0.4
70
70
–
77
–80
70 typ
70
dB min
dB min
dB max
dB max
f
IN
= 10 kHz Sine Wave,
f
SAMPLE
= 100 kHz
f
IN
= 10 kHz Sine Wave,
f
SAMPLE
= 100 kHz
f
IN
= 10 kHz Sine Wave,
f
SAMPLE
= 100 kHz
fa = 9 kHz, fb = 9.5 kHz,
f
SAMPLE
= 100 kHz
–
77
–80
–80 typ
–80 typ
–
77
–
77
–80
12
12
±
1/2
±
1
±
1.5
±
4
±
3
0 to +V
DD
±
2
2.0
2.4
0.8
±
10
10
–80 typ
–80 typ
12
12
±
1
±
1
±
3
±
5
±
5
–
77
–80
12
12
±
1
±
1
±
3
±
4
±
4
dB max
dB max
Bits
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
V
DD
= 5 V
±
10%
V
DD
= 2.7 V to 3.6 V
0 to +V
DD
0 to +V
DD
V
±
2
±
5
µA
max
2.0
2.4
0.8
±
10
10
2.0
2.4
0.8
±
10
10
2.4
0.4
V min
V max
µA
max
pF max
V min
V max
V
DD
= 2.7 V to 3.6 V
V
DD
= 5 V
±
10%
V
IN
= 0 V to V
DD
2.4
2.4
0.4
0.4
Straight (Natural) Binary
I
SOURCE
= 400 A
I
SINK
= 1.6 mA
8
14
1.5
8
14
1.5
8
14
1.5
8.5
14.5
1.5
µs
max
µs
max
µs
max
–2–
Rev. D
AD7896
Parameter
POWER REQUIREMENTS
V
DD
I
DD
A Version
2.7/5.5
4
5
Power Dissipation
Power-Down Mode
I
DD
@ 25°C
T
MIN
to T
MAX
I
DD
@ 25°C
T
MIN
to T
MAX
Power Dissipation @ 25°C
10.8
5
15
50
150
13.5
1
B Version
2.7/5.5
4
5
10.8
5
15
50
150
13.5
J Version
2.7/5.5
4
5
10.8
5 typ
75
50
500
13.5
S Version Unit
2.7/5.5
4
5
10.8
5
75
50
500
13.5
Test Conditions/
Comments
V min/max
mA max
Digital Input @ DGND,
V
DD
= 2.7 V to 3.6 V
mA max
Digital Inputs @ DGND,
V
DD
= 5 V
±
10%
mW max V
DD
= 2.7 V, Typically 9 mW
Digital Inputs @ DGND
µA
max
V
DD
= 2.7 V to 3.6 V
µA
max
V
DD
= 2.7 V to 3.6 V
µA
max
V
DD
= 5 V
±
10%
µA
max
V
DD
= 5 V
±
10%
µW
max
V
DD
= 2.7 V
NOTES
1
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; J Version: 0°C to +70°C; S Version: –55°C to +125°C.
2
Applies to Mode 1 operation. See the section on Operating Modes.
3
See Terminology.
4
Sample tested @ 25°C to ensure compliance.
5
This 14
µs
includes the wake-up time from standby. This wake-up time is timed from the rising edge of
CONVST,
whereas conversion is timed from the falling edge
of
CONVST,
for narrow
CONVST
pulsewidth the conversion time is effectively the wake-up time plus conversion time, hence 14
µs.
This can be seen from Figure 3.
Note that if the
CONVST
pulsewidth is greater than 6
µs,
the effective conversion time will increase beyond 14
µs.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1
(V
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
A, B Versions
40
40
2
40
2
60
3
100
3
10
50
4
J Version
40
40
2
40
2
60
3
100
3
10
50
4
DD
= 2.7 V to 5.5 V, AGND = DGND = 0 V)
S Version
40
45
2
45
2
70
3
110
3
10
50
4
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
Test Conditions/Comments
CONVST
Pulsewidth
SCLK High Pulsewidth
SCLK Low Pulsewidth
Data Access Time after Falling Edge of SCLK
V
DD
= 5 V
±
10%
V
DD
= 2.7 V to 3.6 V
Data Hold Time after Falling Edge of SCLK
Bus Relinquish Time after Falling Edge of SCLK
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.4 V.
2
The SCLK maximum frequency is 10 MHz. Care must be taken when interfacing to account for the data access time, t
4
, and the setup time required for the user’s
processor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See Serial Interface section for more information.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2 V.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
6
, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
1.6mA
TO
OUTPUT
PIN
1.6V
50pF
400 A
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
Rev. D
–3–
AD7896
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C, unless otherwise noted.)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to DGND . . . . . –0.3 V to V
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