D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
NTHD4502N
Power MOSFET
30 V, 3.9 A, Dual N−Channel ChipFETt
Features
•
Planar Technology Device Offers Low R
DS(on)
and Fast Switching Speed
•
Leadless ChipFET Package has 40% Smaller Footprint than TSOP−6.
Ideal Device for Applications Where Board Space is at a Premium.
•
ChipFET Package Exhibits Excellent Thermal Capabilities. Ideal for
Applications Where Heat Transfer is Required.
•
Pb−Free Package is Available
Applications
V
(BR)DSS
30 V
http://onsemi.com
R
DS(on)
TYP
80 mW @ 10 V
3.9 A
110 mW @ 4.5 V
I
D
MAX
•
DC−DC Buck or Boost Converters
•
Low Side Switching
•
Optimized for Battery and Low Side Switching Applications in
Computing and Portable Equipment
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (Note 1)
Steady
State
t
≤
5s
Power Dissipation
(Note 1)
Steady
State
t
≤
5s
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
Pulsed Drain Current
ESD Capability
(Note 3)
T
A
= 25°C
Steady
State
T
A
= 85°C
T
A
= 25°C
P
D
I
DM
ESD−
HBM
T
J
,
T
STG
I
S
T
L
I
D
T
A
= 25°C
T
A
= 85°C
T
A
= 25°C
P
D
T
A
= 25°C
2.1
2.2
1.6
0.64
12
125
−55 to
150
2.5
260
W
A
V
°C
A
°C
A
Symbol
V
DSS
V
GS
I
D
Value
30
±20
2.9
2.1
3.9
1.13
W
Unit
V
V
A
G
1
, G
2
D
1
, D
2
S
1
, S
2
N−Channel MOSFET
ChipFET
CASE 1206A
STYLE 2
PIN
CONNECTIONS
D
1
8
D
1
7
D
2
6
D
2
5
1 S
1
2 G
1
3 S
2
4 G
2
1
2
3
4
MARKING
DIAGRAM
8
7
6
5
C5 M
G
t
p
= 10
ms
C = 100 pF,
R
S
= 1500
W
Operating Junction and Storage Temperature
Source Current (Body Diode)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
C5 = Specific Device Code
M = Month Code
G
= Pb−Free Package
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size
(Cu area = 0.214 in sq).
3. ESD Rating Information: HBM Class 0.
ORDERING INFORMATION
Device
NTHD4502NT1
NTHD4502NT1G
Package
ChipFET
ChipFET
(Pb−Free)
Shipping
†
3000/Tape & Reel
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTHD4502N/D
©
Semiconductor Components Industries, LLC, 2005
1
November, 2005 − Rev. 5
NTHD4502N
THERMAL RESISTANCE RATINGS
Parameter
Junction−to−Ambient – Steady State (Note 4)
Junction−to−Ambient – t
≤
5 s (Note 4)
Junction−to−Ambient – Steady State (Note 5)
Symbol
R
qJA
R
qJA
R
qJA
Max
110
60
195
Unit
°C/W
4. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
5. Surface Mounted on FR4 Board using the minimum recommended pad size (Cu area = 0.214 in sq).
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Parameter
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
(BR)DSS
I
DSS
V
GS
= 0 V, I
D
= 250
mA
V
GS
= 0 V, V
DS
= 24 V
V
GS
= 0 V, V
DS
= 24 V, T
J
= 125°C
Gate−to−Source Leakage Current
ON CHARACTERISTICS
(Note 6)
Gate Threshold Voltage
Drain−to−Source On−Resistance
V
GS(TH)
R
DS(on)
V
GS
= V
DS
, I
D
= 250
mA
V
GS
= 10 V, I
D
= 2.9 A
V
GS
= 4.5 V, I
D
= 2.2 A
Forward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
C
ISS
C
OSS
C
RSS
C
ISS
C
OSS
C
RSS
Q
G(TOT)
Q
G(TH)
Q
GS
Q
GD
Q
G(TOT)
Q
G(TH)
Q
GS
Q
GD
V
GS
= 4.5 V, V
DS
= 24 V,
I
D
= 2.9 A
V
GS
= 10 V, V
DS
= 15 V,
I
D
= 2.9 A
V
GS
= 0 V, f = 1.0 MHz,
V
DS
= 24 V
V
GS
= 0 V, f = 1.0 MHz,
V
DS
= 15 V
140
53
16
135
42
13
3.6
0.3
0.6
0.7
1.9
0.3
0.6
0.9
nC
250
75
25
7.0
nC
pF
pF
g
FS
V
DS
= 15 V, I
D
= 2.9 A
1.0
1.65
78
105
3.8
3.0
85
140
S
V
mW
I
GSS
V
DS
= 0 V, V
GS
=
"20
V
30
36
1.0
10
"100
nA
V
mA
Symbol
Test Conditions
Min
Typ
Max
Units
6. Pulse Test: Pulse Width
v
300
ms,
Duty Cycle
v
2%.
http://onsemi.com
2
NTHD4502N
ELECTRICAL CHARACTERISTICS
(continued)
(T
J
= 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Time
Reverse Recovery Charge
SWITCHING CHARACTERISTICS
(Note 7)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
t
d(ON)
t
r
t
d(OFF)
t
f
t
d(ON)
t
r
t
d(OFF)
t
f
V
GS
= 4.5 V, V
DD
= 24 V,
I
D
= 2.9 A, R
G
= 2.5
W
V
GS
= 10 V, V
DD
= 24 V,
I
D
= 1 A, R
G
= 6
W
6.5
5.4
14.9
1.8
7.8
12.6
9.6
2.8
12
10
25
5.0
ns
ns
V
SD
t
RR
Q
RR
t
RR
Q
RR
V
GS
= 0 V, I
S
= 2.5 A
V
GS
= 0 V, I
S
= 2.9 A,
dI
S
/dt = 100 A/ms
V
GS
= 0 V, I
S
= 1.0 A,
dI
S
/dt = 100 A/ms
0.85
8.6
4.0
8.4
4.0
1.2
V
ns
nC
ns
nC
7. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
3
NTHD4502N
TYPICAL PERFORMANCE CURVES
10
V
GS
= 10, 6, 5, 4.5 & 4.2 V resp.
I
D,
DRAIN CURRENT (AMPS)
8
4V
I
D,
DRAIN CURRENT (AMPS)
3.8 V
3.6 V
6
3.4 V
4
T
J
= 25°C
2
0
0
1
2
3
4
5
3.2 V
3V
2.8 V
2.6 V
6
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
5
4
3
2
1
0
1
25°C
T
J
= −55°C
3
4
5
2
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
6
6
V
DS
≥
10 V
100°C
Figure 1. On−Region Characteristics
R
DS(on),
DRAIN−TO−SOURCE RESISTANCE (W)
R
DS(on),
DRAIN−TO−SOURCE RESISTANCE (W)
0.3
0.25
0.2
0.15
0.1
0.05
0
2
8
9
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
3
4
5
6
7
10
I
D
= 2.9 A
T
J
= 25°C
0.12
Figure 2. Transfer Characteristics
T
J
= 25°C
0.11
V
GS
= 4.5 V
0.10
0.09
V
GS
= 10 V
0.08
0.07
2
3
4
5
6
I
D,
DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.8
R
DS(on),
DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
1.6
1.4
1.2
1.0
0.8
0.6
−50
0.1
−25
0
25
50
75
100
125
150
I
D
= 2.9 A
V
GS
= 10 V
I
DSS
, LEAKAGE (nA)
100
1000
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
V
GS
= 0 V
T
J
= 150°C
10
T
J
= 100°C
1
5
10
15
20
25
30
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
4
京公网安备 11010802033920号
EEWORLD
