P4SMA10A datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > semiconductor> Discrete semiconductor> P4SMA10A

P4SMA10A: Description400 W, UNIDIRECTIONAL, SILICON, TVS DIODE, DO-214AC; Categorysemiconductor Discrete semiconductor; File Size267KB，3 Pages; ManufacturerFORMOSA; Websitehttp://www.formosams.com/

Download Datasheet View All

P4SMA10A Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	P4SMA10A	-	-	View	Buy Now

P4SMA10A Overview

400 W, UNIDIRECTIONAL, SILICON, TVS DIODE, DO-214AC

Preview

Download Datasheet

View All

Glass Passivated Junction Transient Voltage Suppressor

P4SMA SERIES

VOLTAGE-6.8 TO 540 Volts

400 Watt Peak Pulse Power

Formosa MS

SMA/DO-214AC

Features

• For surface mounted applications in order to

optimize board space

• Glass passivated junction

• Built-in strain relief

• Excellent clamping capability

• Low profile package

• Low inductance

• Excellent clamping capability

• Fast response time: typically less than

1.0 ps from 0 volts to BV min

• Typical I

less than 1µA above 10V

• High temperature soldering guaranteed:

250°C/10 seconds at terminals

深

圳

int

0.087 (2.21)

0.070 (1.80)

0.106(2.7)

0.098(2.5)

0.177(4.50)

0.157(3.99)

0.010(0.250)

0.006(0.150)

0.091(2.3)

0.075(1.9)

Mechanical Data

Case: JEDEC DO-214AC Molded plastic

Terminal： Solder plated, solderable per

MIL-STD-750, Method 2026

Polarity: Color band denoted positive end (cathode)

except Bipolar

Standard Packaging: 12mm tape(EIA STD RS-481)

Weight: 0.002 ounces, 0.061 grams

0.060(1.52)

0.030(0.76)

0.008(0.203)MAX.

0.202(5.15)

0.191(4.85)

Dimensions in inches and (millimeters)

DEVICES FOR BIPOLAR APPLICATIONS

For Bidirectional use CA Suffix for types P4SMA6.8CA thru types P4SMA540CA Electrical characteristics apply in both directions.

MAXIMUM RATINGS AND CHARACTERISTICS

Ratings at 25°C ambient temperature unless otherwise specified.

RATING

Peak Pulse Power Dissipation at T

= 25 °C, T

= 1ms (Note 1)

Peak Pulse Current of on 10/1000 µs waveform

(Note 1)

Steady State Power Dissipation at

= 75°C

Lead lengths .375", 9.5mm

(Note 2)

Peak Forward Surge Current, 8.3ms Single Half Sine-wave

Superimposed on Rated Load,

(JEDEC Method)(Note 3)

Operatings and Storage Temperature Range

SYMBOL

PPM

VALUE

Minimum 400

SEE TABLE 1

1.0

-55 +150

UNITS

Watts

Amps

Watts

Amps

°C

(AV)

FSM

, T

STG

NOTES:

1. Non-repetitive current pulse, per Fig.3 and derated above Ta=25 °C per Fig.2.

2. Mounted on 5.0mm

(0.03mm thick) Copper Pads to each termina

3. 8.3ms single half sine-wave, or equivalent square wave, Duty cycle=4 pulses per minutes maximum.

http://www.formosams.com/

TEL:886-2-22696661

FAX:886-2-22696141

Document ID

Issued Date

2008/02/10

Revised Date

2010/03/10

Revision

Page.

Page 1

DS-222645

Recommended Resources

Asynchronous motor protection circuit composed of photoelectric coupler

Series DC regulated power supply

Sample signal hold circuit

4-20MA－Convert to multiple 5V conversion circuit diagram

NORELCO rechargeable electric shaver circuit

Computer motherboard circuit diagram 815 3_02

[Third Batch of Shortlist] GigaDevice GD32L233 Review Activity: [Review details] Try GigaDevice GD32L233 and start the energy-saving "chip" era![Date for receiving the prize] Please be sureto complete the prize confirmation according to the prize confirmation proc...; EEWORLD社区 GD32 MCU

altera opencl sdk license: I would like to ask you experts, how can I download the license of Altera OpenCL SDK? I am doing my undergraduate thesis, urgently need it! Also, if I use Linux system, which development boards suppor...; moningWYL FPGA/CPLD

Issues about clock constraints in synchronously designed FPGA programs: Questions about clock constraints in synchronously designed FPGA programs?There are several issues that need to be paid attention to during the design process. How many clocks does the entire design r...; eeleader FPGA/CPLD

FPGA Encryption Solution: FPGA encryption solution QQ: 344383284...; 阿里波特 Industrial Control Electronics

FPGA Design Summary - Review!: 1) The timing of the interface between FPGA and other circuits should be handled well, and the line delay before the signal enters the FPGA should be taken into account. The phase relationship between...; eeleader FPGA/CPLD

Personal sensor trends: I think the future trends of sensors are: (1) networking (2) artificial intelligence and expert systemization (3) self-generation. I hope everyone will give their opinions....; besk Sensor

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components