which provides system wide reduction of EMI of all clock
dependent signals. The P2041A allows significant system
cost savings by reducing the number of circuit board layers
and shielding that are traditionally required to pass EMI
regulations.
The P2041A uses the most efficient and optimized
modulation
profile
approved
by
the
FCC
and
is
implemented in a proprietary all-digital method.
The P2041A modulates the output of a single PLL in order
to “spread” the bandwidth of a synthesized clock and, more
importantly,
decreases
the
peak
amplitudes
of
its
harmonics. This result in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called “spread
spectrum clock generation”.
Product Description
The P2041A is a selectable spread spectrum frequency
modulator designed specifically for PC peripheral and
embedded controller markets. The
P2041A reduces
electromagnetic interference (EMI) at the clock source
Applications
The P2041A is targeted towards the embedded controller
market and PC peripheral markets including scanners,
MFP’s, printers, PDA, IA , and GPS devices.
Block Diagram
SR0
SR1
SSON
VDD
Modulation
XIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
January 2006
rev 0.1
Pin Configuration
P2041A
XIN/CLK
XOUT
SR1
VSS
1
1
2
2
33
4
4
8
8
7
7
6
6
5
5
VDD
SR0
ModOUT
SSON
P2041A
P2040C
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN/CLK
XOUT
SR1
VSS
SSON
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
Connect to crystal or externally generated clock signal.
Connect to crystal. No connect if externally generated clock signal is used.
Digital logic input used to select Spreading Range (see Table 1).
This pin has an internal pull-up resistor.
Ground Connection. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active Low). Spread
Spectrum function enable when low. This pin has an internal pull-low resistor.
Spread Spectrum Clock Output.
Digital logic input used to select Spreading Range (see Table 1).
This pin has an internal pull-up resistor.
Connect to +3.3V or +5.0V
Table 1 - Spread Range Selection
SR1
0
0
1
1
SR0
0
1
0
1
Spreading Range
+/- 1.50%
+/- 2.50%
+/- 0.50%
+/- 1.00%
Modulation rate
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz
Versatile EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 9
January 2006
rev 0.1
Spread spectrum selection
P2041A
Table 1 illustrates the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest
without affecting system performance. The spreading is described as a percentage deviation of the center frequency
( Note: the center frequency is the frequency of the external reference input on XIN/CLK, Pin 1).
Example of a typical printer or scanner application that operates on a clock frequency of 40MHz:
A spreading selection of SR1=1 and SR0=1 provides a percentage deviation of +/-1.00%* (see Table 1) of Center
Frequency. This results in the frequency on ModOUT being swept from 40.40MHz to 39.60MHz at a modulation rate of
(40/40)*34.72 = 34.72KHz (see Table 1). This particular example (see Figure below) given here is a common EMI reduction
method for scanners and has already been implemented by most of the leading manufacturers.
NOTE:
Spreading range selection varies from different system manufacturers and their designs. The spreading range of P2041A can be set to +/-2.5% when
working with certain scanner model.
P2041A Application Schematic for Flat-Bed Scanner
40MHz
1 XIN/CLK
2 XOUT
3 SR1
4 VSS
VDD 8
SR0 7
0.1µF
VDD
Modulated 40MHz signal with ± 1.00%
Deviation and modulation rate of
34.72KHz. This signal is connected back
to the clock crystal Input pin of the
system ASIC.
NOTE: The above schematic indicates
The exact setting of this example:
Default setting (no connection on pin 3,
7 and 5)
ModOUT 6
SSON 5
P2041A
Versatile EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 9
January 2006
rev 0.1
Absolute Maximum Ratings
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
P2041A
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +7.0
-65 to +125
-40 to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated)
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
VDD
Input low Voltage
Input low Voltage
Parameter
( For 3.3V Supply Voltage)
( For 5V Supply Voltage)
( For 3.3V Supply Voltage)
( For 5V Supply Voltage)
Min
VSS –0.3
-
2.0
3.5
-
-
-
-
-
-
-
-
2.5
4.5
-
-
-
2.7
Typ
-
-
-
-
-
-
-
-
3
3
-
-
-
-
1.0
-
-
3.3
Max
0.8
1.5
VDD + 0.3
-
-35
-100
35
100
-
-
0.4
0.5
-
-
-
22
35
5.5
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
Input Low Current
( For 3.3V Supply Voltage)
(pull-up resistor on inputs
( For 5V Supply Voltage)
SR0, SR1)
Input High Current
( For 3.3V Supply Voltage)
(pull-down resistor on input
( For 5V Supply Voltage)
SSON )
XOUT Output Low Current (V
XOL
@ 0.4V, VDD = 3.3V)
XOUT Output High Current ( V
XOH
@ 2.5V, VDD = 3.3V)
Output Low Voltage
Output High Voltage
Static Supply Current
Dynamic Supply Current
Operating Voltage
3.3V and 15pF loading
5V and 15pF loading
(VDD=3.3V, I
OL
= 20 mA)
(VDD=5V, I
OL
= 20 mA)
(VDD=3.3V, I
OH
= 20 mA)
(VDD=5V, I
OH
= 20 mA)
Versatile EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 9
January 2006
rev 0.1
AC Electrical Characteristics
Symbol
f
IN
t
LH
*
t
HL
*
t
JC
t
D
Input Frequency
Output rise time
( Measured at 0.8V to 2.0V )
Output fall time
( Measured at 2.0 to 0.8V )
Jitter (Cycle to cycle)
Output duty cycle
P2041A
Parameter
Min
25
0.7
0.6
-
45
Typ
40
1.0
0.8
360
50
Max
60
1.3
1.0
-
55
Unit
MHz
nS
nS
pS
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF
Versatile EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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