PSMN020-30MLC
4 September 2012
N-channel 30 V 18.1 mΩ logic level MOSFET in LFPAK33
using TrenchMOS Technology
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK33 package. This product
is designed and qualified for use in a wide range of industrial, communications and
domestic equipment.
1.2 Features and benefits
•
Low parasitic inductance and resistance
•
Optimised for 4.5V Gate drive utilising Superjunction technology
•
Ultra low QG, QGD, and QOSS for high system efficiencies at low and high loads
1.3 Applications
•
DC-to-DC converters
•
Load switching
•
Synchronous buck regulator
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
junction temperature
Conditions
T
j
= 25 °C
T
mb
= 25 °C; V
GS
= 10 V;
Fig. 1
T
mb
= 25 °C;
Fig. 2
Min
-
-
-
-55
Typ
-
-
-
-
Max
30
31.8
33
175
Unit
V
A
W
°C
Static characteristics
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 5 A; T
j
= 25 °C;
Fig. 10
V
GS
= 10 V; I
D
= 5 A; T
j
= 25 °C;
Fig. 10
Dynamic characteristics
Q
GD
Q
G(tot)
gate-drain charge
total gate charge
V
GS
= 4.5 V; I
D
= 5 A; V
DS
= 15 V;
Fig. 12; Fig. 13
V
GS
= 4.5 V; I
D
= 5 A; V
DS
= 15 V;
Fig. 12; Fig. 13
-
4.6
-
nC
-
1.7
-
nC
-
14.7
18.1
mΩ
-
20.5
27
mΩ
Scan or click this QR code to view the latest information for this product
NXP Semiconductors
PSMN020-30MLC
N-channel 30 V 18.1 mΩ logic level MOSFET in LFPAK33 using
TrenchMOS Technology
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning information
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
1
2
3
4
G
mbb076
Simplified outline
Graphic symbol
D
S
LFPAK33 (SOT1210)
3. Ordering information
Table 3.
Ordering information
Package
Name
PSMN020-30MLC
LFPAK33
Description
Plastic single ended surface mounted package (LFPAK33); 4
leads
Version
SOT1210
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
I
D
Parameter
drain-source voltage
gate-source voltage
drain current
V
GS
= 10 V; T
mb
= 25 °C;
Fig. 1
V
GS
= 10 V; T
mb
= 100 °C;
Fig. 1
I
DM
P
tot
T
stg
T
j
T
sld(M)
V
ESD
I
S
I
SM
peak drain current
total power dissipation
storage temperature
junction temperature
peak soldering temperature
electrostatic discharge voltage
MM (JEDEC JESD22-A115)
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C;
Fig. 4
T
mb
= 25 °C;
Fig. 2
Conditions
T
j
= 25 °C
Min
-
-20
-
-
-
-
-55
-55
-
130
Max
30
20
31.8
22.5
127
33
175
175
260
-
Unit
V
V
A
A
A
W
°C
°C
°C
V
Source-drain diode
source current
peak source current
T
mb
= 25 °C
pulsed; t
p
≤ 10 µs; T
mb
= 25 °C
-
-
27.4
127
A
A
PSMN020-30MLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
4 September 2012
2 / 13
NXP Semiconductors
PSMN020-30MLC
N-channel 30 V 18.1 mΩ logic level MOSFET in LFPAK33 using
TrenchMOS Technology
Symbol
E
DS(AL)S
Parameter
non-repetitive drain-source
avalanche energy
Conditions
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 31 A;
V
sup
≤ 30 V; R
GS
= 50 Ω; unclamped;
Fig. 3
Min
-
Max
7.7
Unit
mJ
Avalanche ruggedness
I
D
(A)
40
003aak267
120
P
der
(%)
80
03na19
30
20
40
10
0
0
30
60
90
120
150
T
j
(°C)
180
0
0
50
100
150
T
mb
(°C)
200
Fig. 1.
Continuous drain current as a function of
mounting base temperature
Fig. 2.
Normalized total power dissipation as a
function of mounting base temperature
I
AL
(A)
10
2
003aak268
10
(1)
1
(2)
10
-1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig. 3.
Single pulse avalanche rating; avalanche current as a function of avalanche time
PSMN020-30MLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
4 September 2012
3 / 13
NXP Semiconductors
PSMN020-30MLC
N-channel 30 V 18.1 mΩ logic level MOSFET in LFPAK33 using
TrenchMOS Technology
I
D
(A)
10
3
003aak269
10
2
Limit R
DSon
= V
DS
/ I
D
t
p
= 10 us
10
DC
1
100 us
1 ms
10 ms
100 ms
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig. 4.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
thermal resistance
from junction to
mounting base
10
Conditions
Fig. 5
Min
-
Typ
4.32
Max
4.56
Unit
K/W
003aak270
Z
th(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
0.05
10
-1
0.02
single shot
P
δ=
t
p
T
t
p
10
-2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
T
t
p
(s)
1
Fig. 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN020-30MLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved
Product data sheet
4 September 2012
4 / 13
NXP Semiconductors
PSMN020-30MLC
N-channel 30 V 18.1 mΩ logic level MOSFET in LFPAK33 using
TrenchMOS Technology
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
Conditions
I
D
= 13.5 A; V
GS
= 0 V; T
j(init)
= 25 °C;
t
p
≤ 50 µs
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
V
GS(th)
ΔV
GS(th)
/ΔT
gate-source threshold
voltage
gate-source threshold
voltage variation with
temperature
drain leakage current
V
DS
= 30 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 30 V; V
GS
= 0 V; T
j
= 150 °C
I
GSS
gate leakage current
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
R
DSon
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 5 A; T
j
= 25 °C;
Fig. 10
V
GS
= 4.5 V; I
D
= 5 A; T
j
= 150 °C;
Fig. 10; Fig. 11
V
GS
= 10 V; I
D
= 5 A; T
j
= 25 °C;
Fig. 10
V
GS
= 10 V; I
D
= 5 A; T
j
= 150 °C;
Fig. 10; Fig. 11
R
G
Q
G(tot)
gate resistance
f = 1 MHz
0.68
1.37
2.74
Ω
-
-
14.7
-
18.1
29
mΩ
mΩ
-
-
43.2
mΩ
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C
30
27
1.05
-
-
-
1.62
-3.5
-
-
1.95
-
V
V
V
mV/K
Min
34
Typ
-
Max
-
Unit
V
Static characteristics
I
DSS
-
-
-
-
-
-
-
-
-
20.5
1
100
100
100
27
µA
µA
nA
nA
mΩ
Dynamic characteristics
total gate charge
I
D
= 5 A; V
DS
= 15 V; V
GS
= 10 V;
Fig. 12; Fig. 13
I
D
= 5 A; V
DS
= 15 V; V
GS
= 4.5 V;
Fig. 12; Fig. 13
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V
Q
GS
Q
GS(th)
Q
GS(th-pl)
Q
GD
V
GS(pl)
PSMN020-30MLC
-
-
-
-
-
-
-
9.5
4.6
8.4
1
0.3
0.7
1.7
2.4
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
nC
nC
V
gate-source charge
pre-threshold gate-
source charge
post-threshold gate-
source charge
gate-drain charge
gate-source plateau
voltage
I
D
= 5 A; V
DS
= 15 V; V
GS
= 4.5 V;
Fig. 12; Fig. 13
I
D
= 5 A; V
DS
= 15 V;
Fig. 12; Fig. 13
All information provided in this document is subject to legal disclaimers.
-
© NXP B.V. 2012. All rights reserved
Product data sheet
4 September 2012
5 / 13
京公网安备 11010802033920号
EEWORLD
