PHK5NQ15T
2 August 2013
SO
8
N-channel TrenchMOS standard level FET
Product data sheet
1. General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
2. Features and benefits
•
Low conduction losses due to low on-state resistance
3. Applications
•
•
DC-to-DC convertors switching
General purpose switching
4. Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
Conditions
T
j
≥ 25 °C; T
j
≤ 150 °C
T
sp
= 25 °C; V
GS
= 10 V;
Fig. 1; Fig. 3
T
sp
= 25 °C;
Fig. 2
V
GS
= 10 V; I
D
= 5 A; T
j
= 25 °C;
Fig. 9;
Fig. 10
V
GS
= 10 V; I
D
= 5 A; V
DS
= 75 V;
T
j
= 25 °C;
Fig. 11
-
12
-
nC
Min
-
-
-
Typ
-
-
-
Max
150
5
6.25
Unit
V
A
W
Static characteristics
drain-source on-state
resistance
-
56
75
mΩ
Dynamic characteristics
Q
GD
gate-drain charge
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NXP Semiconductors
PHK5NQ15T
N-channel TrenchMOS standard level FET
5. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
S
S
S
G
D
D
D
D
source
source
source
gate
drain
drain
drain
drain
1
4
G
mbb076
Simplified outline
8
5
Graphic symbol
D
S
SO8 (SOT96-1)
6. Ordering information
Table 3.
Ordering information
Package
Name
PHK5NQ15T
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Type number
7. Marking
Table 4.
Marking codes
Marking code
K5NQ15T
Type number
PHK5NQ15T
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
DGR
V
GS
I
D
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
sp
= 100 °C; V
GS
= 10 V;
Fig. 1
T
sp
= 25 °C; V
GS
= 10 V;
Fig. 1; Fig. 3
I
DM
P
tot
PHK5NQ15T
Conditions
T
j
≥ 25 °C; T
j
≤ 150 °C
T
j
≥ 25 °C; T
j
≤ 150 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
Max
150
150
20
3.23
5
20
6.25
Unit
V
V
V
A
A
A
W
peak drain current
total power dissipation
T
sp
= 25 °C; pulsed; t
p
≤ 10 µs;
Fig. 3
T
sp
= 25 °C;
Fig. 2
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© NXP N.V. 2013. All rights reserved
Product data sheet
2 August 2013
2 / 12
NXP Semiconductors
PHK5NQ15T
N-channel TrenchMOS standard level FET
Symbol
T
stg
T
j
I
S
I
SM
120
I
der
(%)
80
Parameter
storage temperature
junction temperature
Conditions
Min
-55
-55
Max
150
150
Unit
°C
°C
Source-drain diode
source current
peak source current
T
sp
= 25 °C
T
sp
= 25 °C; pulsed; t
p
≤ 10 µs
03aa25
-
-
5
20
03aa17
A
A
120
P
der
(%)
80
40
40
0
0
50
100
150
T
sp
(°C)
200
0
0
50
100
150
T
sp
(°C)
200
Fig. 1.
Normalized continuous drain current as a
function of solder point temperature
Fig. 2.
Normalized total power dissipation as a
function of solder point temperature
10
2
I
D
(A)
10
t
p
=10 µ s
100 µ s
003aag937
Limit R
DSon
= V
DS
/ I
D
1
DC
10
-1
10 ms
100 ms
10
-2
10
-1
1
10
10
2
V
DS
(V)
10
3
Fig. 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHK5NQ15T
All information provided in this document is subject to legal disclaimers.
© NXP N.V. 2013. All rights reserved
Product data sheet
2 August 2013
3 / 12
NXP Semiconductors
PHK5NQ15T
N-channel TrenchMOS standard level FET
9. Thermal characteristics
Table 6.
Symbol
R
th(j-sp)
Thermal characteristics
Parameter
thermal resistance
from junction to solder
point
thermal resistance
from junction to
ambient
Conditions
Fig. 4
Min
-
Typ
-
Max
20
Unit
K/W
R
th(j-a)
minimum footprint ; mounted on
printed-circuit board
-
70
-
K/W
10
2
Z
th(j-sp)
(K/W)
10
δ = 0.5
0.2
0.1
1
0.05
0.02
single pulse
10
- 1
t
p
10
- 2
10
- 4
10
- 3
10
- 2
10
- 1
1
P
003aaa243
δ=
t
p
T
t
T
10
t
p
(s)
Fig. 4.
Transient thermal impedance from junction to ambient as a function of pulse duration
10. Characteristics
Table 7.
Symbol
V
(BR)DSS
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
Fig. 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C;
Fig. 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
Fig. 8
I
DSS
drain leakage current
V
DS
= 120 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 120 V; V
GS
= 0 V; T
j
= 150 °C
I
GSS
PHK5NQ15T
Min
134
150
-
1.2
2
-
-
-
Typ
-
-
-
-
3
-
-
10
Max
-
-
4.5
-
4
1
100
100
Unit
V
V
V
V
V
µA
µA
nA
Static characteristics
V
GS(th)
gate leakage current
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
All information provided in this document is subject to legal disclaimers.
© NXP N.V. 2013. All rights reserved
Product data sheet
2 August 2013
4 / 12
NXP Semiconductors
PHK5NQ15T
N-channel TrenchMOS standard level FET
Symbol
R
DSon
Parameter
drain-source on-state
resistance
Conditions
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 5 A; T
j
= 150 °C;
Fig. 9; Fig. 10
V
GS
= 5 V; I
D
= 3 A; T
j
= 25 °C
V
GS
= 10 V; I
D
= 5 A; T
j
= 25 °C;
Fig. 9;
Fig. 10
Min
-
-
-
-
-
Typ
10
129
60
56
1.9
Max
100
173
80
75
3.8
Unit
nA
mΩ
mΩ
mΩ
Ω
R
G
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
gate resistance
f = 1 MHz
Dynamic characteristics
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
V
DS
= 75 V; R
L
= 15 Ω; V
GS
= 10 V;
R
G(ext)
= 6 Ω; T
j
= 25 °C; I
D
= 5 A
V
DS
= 25 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C;
Fig. 12
I
D
= 5 A; V
DS
= 75 V; V
GS
= 10 V;
T
j
= 25 °C;
Fig. 11
-
-
-
-
-
-
-
-
-
-
29
3
12
1150
187
61
12
12
35
18
41
-
-
1553
252
85
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
Source-drain diode
source-drain voltage
reverse recovery time
recovered charge
I
S
= 5 A; V
GS
= 0 V; T
j
= 25 °C;
Fig. 13
I
S
= 5 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 90 V; T
j
= 25 °C
-
-
-
0.8
87
162
1.2
113
-
V
ns
nC
PHK5NQ15T
All information provided in this document is subject to legal disclaimers.
© NXP N.V. 2013. All rights reserved
Product data sheet
2 August 2013
5 / 12
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