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Datasheet> All Categories > Discrete semiconductor> The transistor> PHP21N06LT
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PHP21N06LT

Description
Power Field-Effect Transistor
CategoryDiscrete semiconductor    The transistor   
File Size229KB，12 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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PHP21N06LT Overview

Power Field-Effect Transistor

PHP21N06LT Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionFLANGE MOUNT, R-PSFM-T3
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresLOGIC LEVEL COMPATIBLE
Avalanche Energy Efficiency Rating (Eas)34 mJ
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage55 V
Maximum drain current (ID)19 A
Maximum drain-source on-resistance0.075 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PSFM-T3
JESD-609 codee3
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formFLANGE MOUNT
Polarity/channel typeN-CHANNEL
Maximum pulsed drain current (IDM)76 A
surface mountNO
Terminal surfaceMatte Tin (Sn)
Terminal formTHROUGH-HOLE
Terminal locationSINGLE
transistor applicationsSWITCHING
Transistor component materialsSILICON

PHP21N06LT Preview

Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
salesaddresses@nexperia.com).
Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
Logic level FET
FEATURES
•
’Trench’
technology
• Low on-state resistance
• Fast switching
• Logic level compatible
g
PHP21N06LT, PHB21N06LT
PHD21N06LT
QUICK REFERENCE DATA
d
SYMBOL
V
DSS
= 55 V
I
D
= 19 A
R
DS(ON)
≤
75 mΩ (V
GS
= 5 V)
R
DS(ON)
≤
70 mΩ (V
GS
= 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB21N06LT is supplied in the SOT404 (D
2
PAK) surface mounting package.
The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
PIN
1
2
3
tab
DESCRIPTION
gate
drain
1
source
SOT78 (TO220AB)
tab
SOT404 (D
2
PAK)
tab
SOT428 (DPAK)
tab
2
1 23
2
1
3
1
3
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Pulsed gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
j
≤
150˚C
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
±
15
±
20
19
13
76
56
175
UNIT
V
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
August 1999
1
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
Logic level FET
AVALANCHE ENERGY LIMITING VALUES
PHP21N06LT, PHB21N06LT
PHD21N06LT
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
Non-repetitive avalanche
energy
Peak non-repetitive
avalanche current
CONDITIONS
Unclamped inductive load, I
AS
= 9.7 A;
t
p
= 100
µs;
T
j
prior to avalanche = 25˚C;
V
DD
≤
25 V; R
GS
= 50
Ω;
V
GS
= 5 V; refer to
fig:15
MIN.
-
MAX.
34
UNIT
mJ
I
AS
-
19
A
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
TYP.
-
SOT78 package, in free air
SOT428 and SOT404 package, pcb
mounted, minimum footprint
60
50
MAX.
2.7
-
-
UNIT
K/W
K/W
K/W
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
GS(TO)
R
DS(ON)
g
fs
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
GS
= 10 V; I
D
= 10 A
V
GS
= 5 V; I
D
= 10 A
T
j
= 175˚C
Forward transconductance
V
DS
= 25 V; I
D
= 10 A
Gate source leakage current V
GS
=
±5
V; V
DS
= 0 V
Zero gate voltage drain
V
DS
= 55 V; V
GS
= 0 V;
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
I
D
= 20 A; V
DD
= 44 V; V
GS
= 5 V
MIN.
55
50
1.0
0.5
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
1.5
-
-
55
60
-
13
10
0.05
-
9.4
2.2
5.4
7
88
25
25
3.5
4.5
7.5
466
95
71
-
-
2.0
-
2.3
70
75
158
-
100
10
500
-
-
-
15
120
40
45
-
-
-
650
135
85
V
V
V
V
V
mΩ
mΩ
mΩ
S
nA
µA
µA
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
pF
pF
pF
T
j
= 175˚C
V
DD
= 30 V; R
D
= 1.2
Ω;
R
G
= 10
Ω;
V
GS
= 5 V
Resistive load
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
August 1999
2
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
-
I
F
= 20 A; V
GS
= 0 V
I
F
= 20 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= 30 V
-
-
-
TYP. MAX. UNIT
-
-
1.2
43
94
19
76
1.5
-
-
A
A
V
ns
nC
Normalised Power Derating, PD (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
100
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
tp = 10 us
10
100 us
1 ms
10 ms
100 ms
D.C.
1
0.1
1
10
Drain-Source Voltage, VDS (V)
100
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Transient thermal impedance, Zth j-mb (K/W)
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
10
D = 0.5
1
0.2
0.1
0.05
0.1
0.02
single pulse
T
0.01
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
P
D
tp
D = tp/T
Pulse width, tp (s)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
August 1999
3
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOS™ transistor
Logic level FET
PHP21N06LT, PHB21N06LT
PHD21N06LT
35
30
25
20
15
10
5
0
0
Drain Current, ID (A)
Tj = 25 C
VGS = 10V
5V
3.4 V
3.2 V
3V
2.8 V
2.6 V
2.4 V
0.2
0.4
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VDS (V)
1.6
1.8
2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Transconductance, gfs (S)
VDS > ID X RDS(ON)
Tj = 25 C
175 C
0
2
4
6
8
10
12
14
Drain current, ID (A)
16
18
20
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
)
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
)
Normalised On-state Resistance
0.3
0.25
Drain-Source On Resistance, RDS(on) (Ohms)
2.6 V
2.4 V
2.8V
Tj = 25 C
0.2
0.15
0.1
0.05
3V
3.2 V
3.4 V
5V
VGS = 10V
0
0
5
10
15
20
Drain Current, ID (A)
25
30
35
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-60
-40
-20
0
20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
Threshold Voltage, VGS(TO) (V)
maximum
Drain current, ID (A)
20
18
16
14
12
10
8
6
4
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Gate-source voltage, VGS (V)
175 C
Tj = 25 C
VDS > ID X RDS(ON)
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
typical
minimum
-60
-40 -20
0
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
August 1999
4
Rev 1.500
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PHP21N06LT PHB21N06LT PHB21N06LTT/R PHB21N06LT/T3 PHB21N06LT-T PHD21N06LT PHD21N06LT/T3 934055349118 934054570118
Description Power Field-Effect Transistor Power Field-Effect Transistor Power Field-Effect Transistor Power Field-Effect Transistor Power Field-Effect Transistor Power Field-Effect Transistor Power Field-Effect Transistor Power Field-Effect Transistor Power Field-Effect Transistor
Maker Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia
package instruction FLANGE MOUNT, R-PSFM-T3 SMALL OUTLINE, R-PSSO-G2 D2PAK-3 SMALL OUTLINE, R-PSSO-G2 SMALL OUTLINE, R-PSSO-G2 DPAK-3 DPAK-3 SMALL OUTLINE, R-PSSO-G2 SMALL OUTLINE, R-PSSO-G2
Reach Compliance Code compliant not_compliant not_compliant compliant compliant compliant unknown compliant not_compliant
Other features LOGIC LEVEL COMPATIBLE LOGIC LEVEL COMPATIBLE LOGIC LEVEL COMPATIBLE LOGIC LEVEL COMPATIBLE LOGIC LEVEL COMPATIBLE LOGIC LEVEL COMPATIBLE LOGIC LEVEL COMPATIBLE LOGIC LEVEL COMPATIBLE LOGIC LEVEL COMPATIBLE
Avalanche Energy Efficiency Rating (Eas) 34 mJ 34 mJ 34 mJ 34 mJ 34 mJ 34 mJ 34 mJ 34 mJ 34 mJ
Shell connection DRAIN DRAIN DRAIN DRAIN DRAIN DRAIN DRAIN DRAIN DRAIN
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 55 V 55 V 55 V 55 V 55 V 55 V 55 V 55 V 55 V
Maximum drain current (ID) 19 A 19 A 19 A 19 A 19 A 19 A 19 A 19 A 19 A
Maximum drain-source on-resistance 0.075 Ω 0.075 Ω 0.075 Ω 0.075 Ω 0.075 Ω 0.075 Ω 0.075 Ω 0.075 Ω 0.075 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 code R-PSFM-T3 R-PSSO-G2 R-PSSO-G2 R-PSSO-G2 R-PSSO-G2 R-PSSO-G2 R-PSSO-G2 R-PSSO-G2 R-PSSO-G2
Number of components 1 1 1 1 1 1 1 1 1
Number of terminals 3 2 2 2 2 2 2 2 2
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form FLANGE MOUNT SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Polarity/channel type N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL N-CHANNEL
Maximum pulsed drain current (IDM) 76 A 76 A 76 A 76 A 76 A 76 A 76 A 76 A 76 A
surface mount NO YES YES YES YES YES YES YES YES
Terminal form THROUGH-HOLE GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal location SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE
transistor applications SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON SILICON SILICON SILICON SILICON SILICON SILICON SILICON SILICON
Is it Rohs certified? conform to conform to conform to - - conform to conform to conform to conform to
JESD-609 code e3 e3 e3 - - e3 - - e3
Terminal surface Matte Tin (Sn) Tin (Sn) Tin (Sn) - - TIN - - Tin (Sn)
Peak Reflow Temperature (Celsius) - 245 245 - - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED -
Maximum time at peak reflow temperature - 30 NOT SPECIFIED - - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED -

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Shortcut:   A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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