A product Line of
Diodes Incorporated
PI3PCIE3415A
3.3V, PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch
Features
ÎÎ
Differential Channel, 2:1 Mux/DeMux
4
ÎÎ
PCI Express
®
3.0 Performance, 8.0Gbps
ÎÎ
Pinout optimized for placement between two PCIe slots
ÎÎ
Bi-directional operation
ÎÎ
Low Bit-to-Bit Skew, 10ps max
ÎÎ
Low Crosstalk: -48dB @4GHz
ÎÎ
High Off Isolation:
ÎÎ
Return Loss:
Description
The PI3PCIE3415A is an 8 to 4 differential channel multiplexer/
demultiplexer switch. This solution can switch 2 full PCI Ex-
press® 3.0, lanes to one of two locations. Using a unique design
technique, Diodes has been able to minimize the impedance of
the switch such that the attenuation observed through the switch
is negligible. The unique design technique also offers a layout
targeted for PCI Express signals, which minimizes the channel to
channel skew as well as channel to channel crosstalk as required
by the PCI Express specification.
-22dB @4GHz
ÎÎ
Low Insertion Loss: -1.2dB @4GHz
-15dB @4GHz
o
ÎÎ
DD
Operating Range: +3.3V
V
ÎÎ
Industrial Temperature Range: -40
ÎÎ
ESD Tolerance: 1.5kV HBM
Application
C to 85 C
o
Routing of PCI Express 3.0, DP1.2, USB3.0, SAS2.0, SATA3.0,
XAUI, RXAUI signals with low signal attenuation.
ÎÎ
Low channel-to-channel skew, 20ps max
ÎÎ
Packaging (Pb-free & Green):
à
42-contact, TQFN (ZH42), 3.5 x 9mm
à
40-contact, TQFN (ZL40), 3 x 6mm
Block Diagram
AI
+
AI
–
BI
+
BI
–
AOa
+
AOa
–
BOa
+
BOa
–
AOb
+
AOb
–
BOb
+
BOb
–
COa
+
COa
–
DOa
+
DOa
–
COb
+
COb
–
DOb
+
DOb
–
SEL
Truth Table
Function
xIy to xOay
xIy to xOby
SEL
L
H
CI
+
CI
–
DI
+
DI
–
PI3PCIE3415A
Document Number DS40126 Rev 1-2
1
www.diodes.com
November 2017
Diodes Incorporated
A product Line of
Diodes Incorporated
PI3PCIE3415A
Pin Description 40-Contact TQFN
(Top-Side View)
Pin Description 42-Contact TQFN
(Top-Side View)
GND
V
DD
GND
V
DD
AI-
AI+
GND
GND
V
DD
GND
AOb+
AOb-
BI+
BI-
BOb+
BOb-
V
DD
GND
CI+
CI-
COb+
COb-
DI+
DI-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
40 39 38 37 36 35
AI+
AI-
34
33
32
31
30
29
28
27
26
25
24
23
22
21
AOa+
AOa-
V
DD
BOa+
BOa-
GND
V
DD
SEL
GND
COa+
COa-
V
DD
DOa+
DOa-
AOb+
AOb-
BI+
BI-
BOb+
BOb-
VDD
CI+
CI-
COb+
COb-
DI+
DI-
DOb+
DOb-
15 16 17 18 19 20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
42 41 40 39
GND
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
GND
AOa+
AOa-
GND
VDD
BOa+
BOa-
VDD
SEL
GND
COa+
COa-
VDD
GND
DOa+
DOa-
GND
GND
DOb+
DOb-
GND
V
DD
GND
18 19 20 21
GND
V
DD
GND
V
DD
www.diodes.com
PI3PCIE3415A
Document Number DS40126 Rev 1-2
2
November 2017
Diodes Incorporated
A product Line of
Diodes Incorporated
PI3PCIE3415A
Signal Descriptions
Pin Number
42-TQFN
1, 2
40-TQFN
39, 40
Pin Name
AI+, AI-
Type
Differential I/O
Description
Differential
I/O
pair from PCIE signal source. Signal is
routed to the AOa+, AOa- pin respectively when SEL=0.
Signal is routed to the AOb+, AOb- pin respectively when
SEL = 1.
Differential analog pass-through
I/O
. Signal from AI+ and
AI- is routed to AOa+ and AOa- respectively when SEL=0.
Differential analog pass-through
I/O
. Signal from AI+ and
AI- is routed to AOb+ and AOb- respectively when SEL=1.
Differential
I/O
pair from PCIE signal source. Signal is
routed to the BOa+, BOa- pin respectively when SEL=0.
Signal is routed to the BOb+, BOb- pin respectively when
SEL = 1.
Differential analog pass-through
I/O
. Signal from BI+ and
BI- is routed to BOa+ and BOa- respectively when SEL=0.
Differential analog pass-through
I/O
. Signal from BI+ and
BI- is routed to BOb+ and BOb- respectively when SEL=1.
Differential
I/O
pair from PCIE signal source. Signal is
routed to the COa+, COa- pin respectively When SEL=0.
Signal is routed to the COb+, COb- pin respectively when
SEL = 1.
Differential analog pass-through
I/O
. Signal from CI+ and
CI- is routed to COa+, COa- pin respectively when SEL = 0.
Differential analog pass-through
I/O
. Signal from CI+ and
CI- is routed to COb+, COb- pin respectively when SEL = 1.
Differential
I/O
pair from PCIE signal source. Signal is
routed to the DOa+, DOa- pin respectively When SEL=0.
Signal is routed to the DOb+, DOb- pin respectively when
SEL = 1.
Differential analog pass-through
I/O
. Signal from DI+ and
DI- is routed to DOa+, DOa- pin respectively when SEL = 0.
Differential analog pass-through
I/O
. Signal from DI+ and
DI- is routed to DOb+, DOb- pin respectively when SEL = 1.
Ground
37, 36
3, 4
34, 33
1, 2
AOa+, AOa-
AOb+, AOb-
Differential I/O
Differential I/O
5, 6
3, 4
BI+, BI-
Differential I/O
33, 32
7, 8
31, 30
5, 6
BOa+, BOa-
BOb+, BOb-
Differential I/O
Differential I/O
10, 11
9, 10
CI+, CI-
Differential I/O
28, 27
12, 13
25, 24
11, 12
COa+, COa-
COb+, COb-
Differential I/O
Differential I/O
14, 15
13, 14
DI+, DI-
Differential I/O
24, 23
16, 17
22, 21
16, 17
DOa+, DOa-
DOb+, DOb-
Differential I/O
Differential I/O
Ground input
18, 20, 22,
15, 18, 20, 26,
25, 29, 35, 38, 29, 35, 37, 38, GND
40, 42
Center Pad
30
9, 19, 21, 26,
31, 34, 39, 41
27
7, 19, 23, 28,
32, 36
SEL
VDD
3.6V tolerant low-voltage
SEL controls the mux through a flow-through latch.
single-ended input
Power supply
Power, 3.3V ±10%
PI3PCIE3415A
Document Number DS40126 Rev 1-2
3
www.diodes.com
November 2017
Diodes Incorporated
A product Line of
Diodes Incorporated
PI3PCIE3415A
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ....................................................–65°C to +150°C
Supply Voltage to Ground Potential ................................–0.5V to +3.7V
Channel DC Input Voltage ................................................ –0.5V to 1.5V
DC Output Current ....................................................................... 120mA
SEL DC Input Voltage ....................................................... –0.5V to 3.7V
Junction Temperature ..................................................................... 125°C
Note: Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extend-
ed periods may affect reliability.
Electrical Characteristics
Recommended Operating Conditions
Symbol
V
DD
I
DD
T
A
Parameter
3.3V Power Supply
Total current from V
DD
3.3V supply
Operating temperature
range
Conditions
Min.
3.0
Typ.
3.3
0.15
Max.
3.6
1
85
Units
V
mA
o
C
SEL = 0V or V
DD
0
-40
DC Electrical Characteristics
(T
A
= –40°C to +85°C, V
DD
= 3.3V ± 10%)
Parameter
V
IH-SEL
V
IL-SEL
I
IN_SEL
I
IH
I
IL
I
IH
I
IL
I
OZH
I
OZL
Note:
1. Typical values are at V
DD
= 3.3V, T
A
= 25°C ambient and maximum loading.
Description
Input high level, SEL input
Input Low Level, SEL input
Input Leakage Current,
SEL input
Input High Current,
xI, xO
Input Low Current,
xI, xO
Input High Current,
SEL
Input Low Current,
SEL
HighZ High Current
xOa, xOb
HighZ Low Current
xOa, xOb
Test Conditions
Min.
2.0
0
Typ.
(1)
Max.
3.6
0.8
10
10
10
5
5
10
10
Units
V
V
uA
uA
uA
uA
uA
uA
uA
Measured with input at VIH-SEL max and
VIL-SEL min
V
DD
= Max, V
IN
= 1.5V
V
DD
= Max, V
IN
= 0V
V
DD
= Max, V
IN
= V
DD
V
DD
= Max, V
IN
= 0V
V
DD
= Max, V
IN
= 1.5V
V
DD
= Max, V
IN
= 0V
–10
–10
–10
–5
–5
–10
–10
PI3PCIE3415A
Document Number DS40126 Rev 1-2
4
www.diodes.com
November 2017
Diodes Incorporated
A product Line of
Diodes Incorporated
PI3PCIE3415A
Dynamic Electrical Characteristics for xI+/-, xOy+/-
Parameter
Description
Test Conditions
f=50MHz -1.25GHz
DDIL
Differential Insertion Loss
f=1.25GHz - 2.5GHz
f=2.5GHz - 4GHz
f=5.0GHz
-25.8
DDIL
OFF
Differential Off Isolation
f= 0 to 4.0GHz
-20.6
-17.6
-15.4
f=50MHz - 1.25GHz
DDRL
Differential Return Loss
f=1.25GHz - 2.5GHz
f=2.5GHz - 4GHz
f=5.0GHz
f=50MHz -1.25GHz
DDNEXT
Near End Crosstalk
f=1.25GHz - 2.5GHz
f=2.5GHz - 4GHz
f=5.0GHz
BW
Bandwidth -3dB
-18.2
-16.8
-12
-8
-44.8
-41.6
-38.4
-36
Min.
Typ.
(1)
-0.8
-1.1
-1.2
-1.7
-32.2
-25.8
-22.0
-19.3
-22.7
-21.0
-15.0
-10.0
-56
-52
-48
-45
8.4
Max.
-1.0
-1.3
-1.5
-2.0
Units
dB
GHz
Switching Characteristics
Parameter
t
PZH
, t
PZL
t
PHZ
, t
PLZ
t
b-b
t
ch-ch
Description
Line Enable Time - SEL to xI+/-, xOy+/-
Line Disable Time - SEL to xI+/-, xOy+/-
Test Conditions
See "Test Circuit for
Electrical Characteristics"
See "Test Circuit for
Electrical Characteristics"
Min.
0.5
0.5
Typ.
15
5
4
Max.
25
25
10
20
Units
ns
ns
ps
ps
Bit-to-bit skew within the same differential See "Test Circuit for
pair
Electrical Characteristics"
Channel-to-channel skew
See "Test Circuit for
Electrical Characteristics"
PI3PCIE3415A
Document Number DS40126 Rev 1-2
5
www.diodes.com
November 2017
Diodes Incorporated
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