PC28F512P30BFB datasheet, PDF - EEWORLD Datasheet

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PC28F512P30BFB: DescriptionFlash, 32MX16, 100ns, PBGA64, BGA-64; Categorystorage storage; File Size1MB，92 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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PC28F512P30BFB Overview

Flash, 32MX16, 100ns, PBGA64, BGA-64

PC28F512P30BFB Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	TBGA, BGA64,8X8,20
Contacts	64
Reach Compliance Code	compli
ECCN code	3A991.B.1.A
Maximum access time	100 ns
Other features	BOTTOM BOOT
startup block	BOTTOM
command user interface	YES
Universal Flash Interface	YES
Data polling	NO
JESD-30 code	R-PBGA-B64
JESD-609 code	e1
length	10 mm
memory density	536870912 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	4,511
Number of terminals	64
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA64,8X8,20
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
page size	16 words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8,1.8/3.3 V
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Department size	16K,64K
Maximum standby current	0.000225 A
Maximum slew rate	0.031 mA
Maximum supply voltage (Vsup)	2 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	NO
type	NOR TYPE
width	8 mm
Base Number Matches	1

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512Mb, 1Gb, 2Gb: P30-65nm

Features

Micron Parallel NOR Flash Embedded

Memory (P30-65nm)

JS28F512P30BFx, JS28F512P30EFx, JS28F512P30TFx,

PC28F512P30BFx, PC28F512P30EFx, PC28F512P30TFx

JS28F00AP30BFx, JS28F00AP30TFx, JS28F00AP30EFx,

PC28F00AP30BFx, PC28F00AP30TFx, PC28F00AP30EFx,

RC28F00AP30BFx, RC28F00AP30TFx, PC28F00BP30EFx

Features

• High performance

• Easy BGA package features

– 100ns initial access for 512Mb, 1Gb Easy BGA

– 105ns initial access for 2Gb Easy BGA

– 25ns 16-word asychronous page read mode

– 52 MHz (Easy BGA) with zero WAIT states and

17ns clock-to-data output synchronous burst

read mode

– 4-, 8-, 16-, and continuous word options for burst

mode

• TSOP package features

– 110ns initial access for 512Mb, 1Gb TSOP

• Both Easy BGA and TSOP package features

– Buffered enhanced factory programming (BEFP)

at 2 MB/s (TYP) using a 512-word buffer

– 1.8V buffered programming at 1.46 MB/s (TYP)

using a 512-word buffer

• Architecture

– MLC: highest density at lowest cost

– Symmetrically blocked architecture (512Mb, 1Gb,

2Gb)

– Asymmetrically blocked architecture (512Mb,

1Gb); four 32KB parameter blocks: top or bottom

configuration

– 128KB main blocks

– Blank check to verify an erased block

• Voltage and power

– V

(core) voltage: 1.7–2.0V

– V

CCQ

(I/O) voltage: 1.7–3.6V

– Standy current: 70µA (TYP) for 512Mb; 75µA

(TYP) for 1Gb

– 52 MHz continuous synchronous read current:

21mA (TYP), 24mA (MAX)

• Security

– One-time programmable register: 64 OTP bits,

programmed with unique information from Mi-

cron; 2112 OTP bits available for customer pro-

gramming

– Absolute write protection: V

= V

– Power-transition erase/program lockout

– Individual zero-latency block locking

– Individual block lock-down

– Password access

• Software

–

25μs

(TYP) program suspend

–

25μs

(TYP) erase suspend

– Flash Data Integrator optimized

– Basic command set and extended function Inter-

face (EFI) command set compatible

– Common flash interface

• Density and Packaging

– 56-lead TSOP package (512Mb, 1Gb)

– 64-ball Easy BGA package (512Mb, 1Gb, 2Gb)

– 16-bit wide data bus

• Quality and reliabilty

– JESD47 compliant

– Operating temperature: –40°C to +85°C

– Minimum 100,000 ERASE cycles per block

– 65nm process technology

PDF: 09005aef845667b3

p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb, 1Gb, 2Gb: P30-65nm

Features

Contents

General Description ......................................................................................................................................... 7

Virtual Chip Enable Description ........................................................................................................................ 8

Memory Map ................................................................................................................................................... 9

Package Dimensions ....................................................................................................................................... 11

Pinouts and Ballouts ....................................................................................................................................... 13

Signal Descriptions ......................................................................................................................................... 15

Bus Operations ............................................................................................................................................... 17

Read .......................................................................................................................................................... 17

Write .......................................................................................................................................................... 17

Output Disable ........................................................................................................................................... 17

Standby ..................................................................................................................................................... 17

Reset .......................................................................................................................................................... 18

Device Command Codes ................................................................................................................................. 19

Device Command Bus Cycles .......................................................................................................................... 22

Read Operations ............................................................................................................................................. 24

Asynchronous Single Word Read ..................................................................................................................... 24

Asynchronous Page Mode Read (Easy BGA Only) ............................................................................................. 24

Synchronous Burst Mode Read (Easy BGA Only) .............................................................................................. 25

Read CFI ........................................................................................................................................................ 25

Read Device ID ............................................................................................................................................... 25

Device ID Codes ............................................................................................................................................. 26

Program Operations ....................................................................................................................................... 27

Word Programming (40h) ........................................................................................................................... 27

Buffered Programming (E8h, D0h) .............................................................................................................. 27

Buffered Enhanced Factory Programming (80h, D0h) ................................................................................... 28

Program Suspend ....................................................................................................................................... 30

Program Resume ........................................................................................................................................ 31

Program Protection .................................................................................................................................... 31

Erase Operations ............................................................................................................................................ 32

BLOCK ERASE Command ........................................................................................................................... 32

BLANK CHECK Command .......................................................................................................................... 32

ERASE SUSPEND Command ....................................................................................................................... 33

ERASE RESUME Command ........................................................................................................................ 33

Erase Protection ......................................................................................................................................... 33

Security Operations ........................................................................................................................................ 34

Block Locking ............................................................................................................................................. 34

BLOCK LOCK Command ............................................................................................................................ 34

BLOCK UNLOCK Command ....................................................................................................................... 34

BLOCK LOCK DOWN Command ................................................................................................................. 34

Block Lock Status ....................................................................................................................................... 34

Block Locking During Suspend ................................................................................................................... 35

Selectable OTP Blocks ................................................................................................................................. 36

Password Access ......................................................................................................................................... 36

Status Register ................................................................................................................................................ 37

Read Status Register ................................................................................................................................... 37

Clear Status Register ................................................................................................................................... 38

Configuration Register .................................................................................................................................... 39

Read Configuration Register ....................................................................................................................... 39

Read Mode ................................................................................................................................................. 39

Latency Count ............................................................................................................................................ 40

PDF: 09005aef845667b3

p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb, 1Gb, 2Gb: P30-65nm

Features

End of Wordline Considerations ..................................................................................................................

WAIT Signal Polarity and Functionality ........................................................................................................

WAIT Delay ................................................................................................................................................

Burst Sequence ..........................................................................................................................................

Clock Edge .................................................................................................................................................

Burst Wrap .................................................................................................................................................

Burst Length ..............................................................................................................................................

One-Time Programmable Registers .................................................................................................................

Read OTP Registers .....................................................................................................................................

Program OTP Registers ...............................................................................................................................

Lock OTP Registers .....................................................................................................................................

Common Flash Interface ................................................................................................................................

READ CFI Structure Output ........................................................................................................................

Flowcharts .....................................................................................................................................................

Power and Reset Specifications .......................................................................................................................

Power Supply Decoupling ...........................................................................................................................

Maximum Ratings and Operating Conditions ..................................................................................................

DC Electrical Specifications ............................................................................................................................

AC Test Conditions and Capacitance ...............................................................................................................

AC Read Specifications ...................................................................................................................................

AC Write Specifications ...................................................................................................................................

Program and Erase Characteristics ..................................................................................................................

Revision History .............................................................................................................................................

Rev. B – 12/13 .............................................................................................................................................

Rev. A – 8/13 ...............................................................................................................................................

PDF: 09005aef845667b3

p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb, 1Gb, 2Gb: P30-65nm

Features

List of Figures

Figure 1: Easy BGA Block Diagram ................................................................................................................... 8

Figure 2: Memory Map – 512Mb and 1Gb ......................................................................................................... 9

Figure 3: Memory Map – 2Gb ......................................................................................................................... 10

Figure 4: 56-Pin TSOP – 14mm x 20mm .......................................................................................................... 11

Figure 5: 64-Ball Easy BGA – 8mm x 10mm x 1.2mm ....................................................................................... 12

Figure 6: 56-Lead TSOP Pinout – 512Mb and 1Gb ........................................................................................... 13

Figure 7: 64-Ball Easy BGA (Top View – Balls Down) – 512Mb, 1Gb, and 2Gb .................................................... 14

Figure 8: Example V

Supply Connections .................................................................................................... 31

Figure 9: Block Locking State Diagram ........................................................................................................... 35

Figure 10: First Access Latency Count ............................................................................................................ 40

Figure 11: Example Latency Count Setting Using Code 3 ................................................................................. 41

Figure 12: End of Wordline Timing Diagram ................................................................................................... 41

Figure 13: OTP Register Map .......................................................................................................................... 46

Figure 14: Word Program Procedure ............................................................................................................... 62

Figure 15: Buffer Program Procedure .............................................................................................................. 63

Figure 16: Buffered Enhanced Factory Programming (BEFP) Procedure ........................................................... 64

Figure 17: Block Erase Procedure ................................................................................................................... 65

Figure 18: Program Suspend/Resume Procedure ............................................................................................ 66

Figure 19: Erase Suspend/Resume Procedure ................................................................................................. 67

Figure 20: Block Lock Operations Procedure ................................................................................................... 68

Figure 21: OTP Register Programming Procedure ............................................................................................ 69

Figure 22: Status Register Procedure .............................................................................................................. 70

Figure 23: Reset Operation Waveforms ........................................................................................................... 72

Figure 24: AC Input/Output Reference Timing ................................................................................................ 76

Figure 25: Transient Equivalent Load Circuit .................................................................................................. 76

Figure 26: Clock Input AC Waveform .............................................................................................................. 76

Figure 27: Asynchronous Single-Word Read (ADV# LOW) ................................................................................ 80

Figure 28: Asynchronous Single-Word Read (ADV# Latch) ............................................................................... 80

Figure 29: Asynchronous Page Mode Read ...................................................................................................... 81

Figure 30: Synchronous Single-Word Array or Nonarray Read .......................................................................... 82

Figure 31: Continuous Burst Read with Output Delay ..................................................................................... 83

Figure 32: Synchronous Burst Mode 4-Word Read ........................................................................................... 84

Figure 33: Write to Write Timing .................................................................................................................... 87

Figure 34: Asynchronous Read to Write Timing ............................................................................................... 87

Figure 35: Write to Asynchronous Read Timing ............................................................................................... 88

Figure 36: Synchronous Read to Write Timing ................................................................................................ 89

Figure 37: Write to Synchronous Read Timing ................................................................................................ 90

PDF: 09005aef845667b3

p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

PC28F512P30BFB Related Products

	PC28F512P30BFB	PC28F512P30TFB
Description	Flash, 32MX16, 100ns, PBGA64, BGA-64	Flash, 32MX16, 100ns, PBGA64, BGA-64
Is it Rohs certified?	conform to	conform to
package instruction	TBGA, BGA64,8X8,20	TBGA, BGA64,8X8,40
Reach Compliance Code	compli	compliant
Maximum access time	100 ns	100 ns
Other features	BOTTOM BOOT	TOP BOOT
startup block	BOTTOM	TOP
command user interface	YES	YES
Universal Flash Interface	YES	YES
Data polling	NO	NO
JESD-30 code	R-PBGA-B64	R-PBGA-B64
JESD-609 code	e1	e1
length	10 mm	10 mm
memory density	536870912 bi	536870912 bit
Memory IC Type	FLASH	FLASH
memory width	16	16
Number of functions	1	1
Number of departments/size	4,511	4,511
Number of terminals	64	64
word count	33554432 words	33554432 words
character code	32000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
organize	32MX16	32MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TBGA	TBGA
Encapsulate equivalent code	BGA64,8X8,20	BGA64,8X8,40
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE	GRID ARRAY, THIN PROFILE
page size	16 words	16 words
Parallel/Serial	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260
power supply	1.8,1.8/3.3 V	1.8,1.8/3.3 V
Programming voltage	3 V	1.8 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm
Department size	16K,64K	16K,64K
Maximum standby current	0.000225 A	0.000225 A
Maximum slew rate	0.031 mA	0.031 mA
Maximum supply voltage (Vsup)	2 V	2 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL
Terminal pitch	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	30
switch bit	NO	NO
type	NOR TYPE	NOR TYPE
width	8 mm	8 mm

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