21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT16501
18-BIT REGISTERED TRANSCEIVERS
PI74LPT16501
Fast CMOS 18-Bit Registered Transceivers
Product Features
• Compatible with LCX™ and LVT™ families of products
• Supports 5V Tolerant Mixed Signal Mode Operation
– Input can be 3V or 5V
– Output can be 3V or connected to 5V bus
• Advanced Low Power CMOS Operation
• Excellent output drive capability:
Balanced drives (24 mA sink and source)
• Pin compatible with industry standard double-density
pinouts
• Low ground bounce outputs
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Multiple center pins and distributed Vcc/GND pins
minimize switching noise
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
1
2
3
4
5
6
7
8
9
10
11
12
Product Description
Pericom Semiconductor’s PI74LPT series of logic circuits are pro-
duced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74LPT16501 is an 18-bit registered bus transceiver designed
with D-type latches and flip-flops to allow data flow in transparent,
latched, and clocked modes. The Output Enable (OEAB and
OEBA, Latch Enable (LEAB and LEBA) and Clock (CLKAB and
CLKBA) inputs control the data flow in each direction. When
LEAB is HIGH, the device operates in transparent mode for A-to-
B data flow. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. The A bus data is stored in
the latch/flip-flop on the LOW-to-HIGH transition of CLKAB, if
LEAB is LOW. OEAB performs the output enable function on the
B port. Data flow from B port to A port is similar using OEBA,
LEBA and CLKBA. This high-speed, low power device offers a
flow-through organization for ease of board layout.
The PI74LPT16501 can be driven from either 3.3V or 5.0V devices
allowing this device to be used as a translator in a mixed
3.3V/5.0V system.
Logic Block Diagram
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
A
1
D
C
B
1
D
13
14
15
C
D
C
D
TO 17 OTHER CHANNELS
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PS2071A 01/16/97
Product Pin Description
Pin Name
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
GND
V
CC
Description
A-to-B Output Enable Input
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
Ground
Power
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LPT16501
18-BIT REGISTERED TRANSCEIVERS
Truth Table
(1,4)
Inputs
OEAB
L
H
H
H
H
H
H
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↑
↑
L
H
Ax
X
L
H
L
H
X
X
Outputs
Bx
Z
L
H
L
H
B
(2)
B
(3)
Product Pin Configuration
OEAB
LEAB
A
0
GND
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
A
17
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
56-PIN
12
V56
13
A56
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
0
GND
B
1
B
2
V
CC
B
3
B
4
B
5
GND
B
6
B
7
B
8
B
9
B
10
B
11
GND
B
12
B
13
B
14
V
CC
B
15
B
16
GND
B
17
CLKBA
GND
Notes:
1. A-to-B data flow is shown. B-to-A data flow is similar but
uses OEBA, LEBA, and CLKBA.
2. Output level before the indicated steady-state input condi-
tions were established.
3. Output level before the indicated steady-state input condi-
tions were established, provided that CLKAB was HIGH
before LEAB went LOW.
4. H = High Voltage Level
L = Low Voltage Level
Z = High Impedance
↑
= LOW-to-HIGH Transition
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PI74LPT16501
18-BIT REGISTERED TRANSCEIVERS
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................. –55°C to +125°C
Ambient Temperature with Power Applied ............................ –40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) ...... –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) .. –0.5V to +7.0V
DC Input Voltage .................................................................... –0.5V to +7.0V
DC Output Current .............................................................................. 120 mA
Power Dissipation .................................................................................... 1.0W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional opera-
tion of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
1
2
3
4
DC Electrical Characteristics
(Over the Operating Range, T
A
= –40°C to +85°C, V
CC
= 2.7V to 3.6V)
Parameters
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
Description
Input HIGH Voltage (Input pins)
Input HIGH Voltage (I/O pins)
Input LOW Voltage
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Min.
2.2
2.0
–0.5
Typ
(2)
—
—
—
—
—
—
—
—
—
–0.7
–60
90
—
3.0
3.0
—
—
0.2
0.3
–85
—
150
Max.
5.5
5.5
0.8
±1
±1
±1
±1
±1
±1
–1.2
–110
200
—
—
—
—
0.2
0.4
0.5
–240
±100
—
Units
V
V
V
µA
µA
µA
µA
µA
µA
V
mA
mA
V
V
V
V
V
V
mA
µA
mV
5
6
7
8
9
10
11
12
13
14
15
V
OL
Output LOW Voltage
I
OS
I
OFF
V
H
Short Circuit Current
(4)
Power Down Disable
Input Hysteresis
V
CC
= Max.
V
IN
= 5.5V
—
V
CC
= Max.
V
IN
= V
CC
—
V
CC
= Max.
V
IN
= GND
—
V
CC
= Max.
V
IN
= GND
—
V
CC
= Max.
V
OUT
= 5.5V
—
V
CC
= Max.
V
OUT
= GND
—
V
CC
= Min., I
IN
= –18 mA
—
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
–36
V
CC
= 3.3V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
50
V
CC
= Min.
I
OH
= –0.1 mA Vcc-0.2
V
IN
= V
IH
or V
IL
I
OH
= –3 mA
2.4
V
CC
= 3.0V,
I
OH
= –8 mA
2.4
(5)
V
IN
= V
IH
or V
IL
I
OH
= –24 mA
2.0
V
CC
= Min.
I
OL
= 0.1 mA
—
V
IN
= V
IH
or V
IL
I
OL
= 16 mA
—
I
OL
= 24 mA
—
(3)
V
CC
= Max. , V
OUT
= GND
–60
V
CC
= 0V, V
IN
or V
OUT
≤
4.5V
—
—
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= V
CC
– 0.6V at rated current.
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PS2071A 01/16/97
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PI74LPT16501
18-BIT REGISTERED TRANSCEIVERS
Power Supply Characteristics
Parameters Description
I
CC
∆I
CC
I
CCD
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
(4)
Test Conditions
(1)
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.,
Outputs Open
X
OE = GND
One Bit Toggling
50% Duty Cycle
V
CC
= Max.,
Outputs Open
f
I
= 10 MH
Z
50% Duty Cycle
X
OE = GND
One Bit Toggling
V
CC
= Max.,
Outputs Open
f
I
= 2.5 MH
Z
50% Duty Cycle
X
OE = GND
16 Bits Toggling
V
IN
= GND or V
CC
V
IN
= V
CC
– 0.6V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
Typ
(2)
0.1
2.0
50
Max.
10
30
75
Units
µA
µA
µA/
MHz
I
C
Total Power Supply
Current
(6)
V
IN
= V
CC
– 0.6V
V
IN
= GND
0.6
2.3
mA
V
IN
= V
CC
– 0.6V
V
IN
= GND
2.1
4.7
(5)
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
I
N
I
)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
I
= Input Frequency
N
I
= Number of Inputs at f
I
All currents are in milliamps and all frequencies are in megahertz.
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PS2071A 01/16/97
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PI74LPT16501
18-BIT REGISTERED TRANSCEIVERS
PI74LPT16501 Switching Characteristics over Operating Range
(1)
LPT16501
Com.
LPT16501A
Com.
Max
Min
(3)
Max
LPT16501C
Com. Preliminary
Min
(3)
Max
Unit
1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameters
t
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
Description
CLKAB or CLKBA frequency
Propagation Delay
A
X
to B
X
or A
X
to B
X
Propagation Delay
LEBA to A
X
, LEAB to B
X
Propagation Delay
CLKBA to A
X
, CLKAB to B
X
Output Enable Time
OEBA to A
X
, OEAB to B
X
Output Disable Time
(4)
OEBA to A
X
, OEAB to B
X
Setup Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Setup Time
HIGH or LOW
Ax to LEAB,
Bx to LEBA
Clock HIGH
Clock LOW
Conditions
(2)
C
L
= 50 pF
R
L
= 500
Ω
Min
(3)
—
1.5
1.5
1.5
1.5
1.5
4.0
0
4.0
1.5
1.5
3.0
3.0
—
100
6.5
7.5
8.0
8.0
7.5
—
—
—
—
—
—
—
0.5
—
1.5
1.5
1.5
1.5
1.5
3.0
0
3.0
1.5
1.5
3.0
3.0
—
150
5.1
5.6
5.6
6.0
5.6
—
—
—
—
—
—
—
0.5
—
1.5
1.5
1.5
1.5
1.5
3.0
0
3.0
1.5
1.5
3.0
3.0
—
150
4.6
5.3
5.3
5.6
5.2
—
—
—
—
—
—
—
0.5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
t
H
t
W
t
W
t
SK
(
O
)
Hold Time HIGH or LOW
Ax to LEAB, Bx to LEBA
LEAB or LEBA Pulse Width
HIGH
(4)
CLKAB or CLKBA Pulse Width
HIGH or LOW
(4)
Output Skew
(5)
Notes:
1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V, extended range, all
Propagation Delays and Enable/Disable times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. This parameter is guaranteed but not production tested.
5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parameters
(1)
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max.
6
8
Units
pF
pF
Note:
1. This parameter is determined by device characterization but is not production tested.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS2071A 01/16/97
Microcontroller MCU
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