MT58L128L18DT-10T datasheet, PDF

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MT58L128L18DT-10T: DescriptionCache SRAM, 128KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100; Categorystorage storage; File Size302KB，17 Pages; ManufacturerCypress Semiconductor

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MT58L128L18DT-10T Overview

Cache SRAM, 128KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026, TQFP-100

MT58L128L18DT-10T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	5 ns
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	2359296 bit
Memory IC Type	CACHE SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX18
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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2Mb: 128K x 18, 64K x 32/36

PIPELINED, DCD SYNCBURST SRAM

2Mb SYNCBURST

SRAM

FEATURES

•

™

MT58L128L18D, MT58L64L32D,

MT58L64L36D

3.3V V

, 3.3V I/O, Pipelined, Double-Cycle Deselect

Fast clock and OE# access times

Single +3.3V +0.3V/-0.165V power supply (V

)

Separate +3.3V isolated output buffer supply (V

SNOOZE MODE for reduced-power standby

Common data inputs and data outputs

Individual BYTE WRITE control and GLOBAL WRITE

Three chip enables for simple depth expansion and

address pipelining

Clock-controlled and registered addresses, data I/Os

and control signals

Internally self-timed WRITE cycle

Burst control pin (interleaved or linear burst)

Automatic power-down for portable applications

100-lead TQFP package for high density, high speed

Low capacitive bus loading

x18, x32 and x36 options available

100-Pin TQFP**

(D-1)

**JEDEC-standard MS-026 BHA (LQFP).

OPTIONS

• Timing (Access/Cycle/MHz)

3.5ns/6ns/166 MHz

4.2ns/7.5ns/133 MHz

5ns/10ns/100 MHz

• Configurations

128K x 18

64K x 32

64K x 36

• Package

100-pin TQFP

MARKING

-6

-7.5

-10

MT58L128L18D

MT58L64L32D

MT58L64L36D

None

synchronous inputs include all addresses, all data inputs,

active LOW chip enable (CE#), two additional chip enables

for easy depth expansion (CE2, CE2#), burst control inputs

(ADSC#, ADSP#, ADV#), byte write enables (BWx#) and

global write (GW#).

Asynchronous inputs include the output enable (OE#),

clock (CLK) and snooze enable (ZZ). There is also a burst

mode pin (MODE) that selects between interleaved and

linear burst modes. The data-out (Q), enabled by OE#, is

also asynchronous. WRITE cycles can be from one to two

bytes wide (x18) or from one to four bytes wide (x32/x36),

as controlled by the write control inputs.

Burst operation can be initiated with either address status

processor (ADSP#) or address status controller (ADSC#)

input pins. Subsequent burst addresses can be internally

generated as controlled by the burst advance pin (ADV#).

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE cycles.

Individual byte enables allow individual bytes to be written.

During WRITE cycles on the x18 device, BWa# controls

DQa pins and DQPa; BWb# controls DQb pins and DQPb.

During WRITE cycles on the x32 and x36 devices, BWa#

controls DQa pins and DQPa; BWb# controls DQb pins and

DQPb; BWc# controls DQc pins and DQPc; BWd# controls

DQd pins and DQPd. GW# LOW causes all bytes to be

written. Parity pins are only available on the x18 and x36

versions.

• Operating Temperature Range

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

*Under consideration.

• Part Number Example: MT58L128L18DT-10 T

GENERAL DESCRIPTION

The Micron

SyncBurst

™

SRAM family employs high-

speed, low-power CMOS designs that are fabricated using

an advanced CMOS process.

Micron’s 2Mb SyncBurst SRAMs integrate a 128K x 18,

64K x 32, or 64K x 36 SRAM core with advanced synchronous

peripheral circuitry and a 2-bit burst counter. All

synchronous inputs pass through registers controlled by a

positive-edge-triggered single clock input (CLK). The

2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM

MT58L128L18D.p65 – Rev. 7/99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Micron Technology, Inc.

All registered and unregistered trademarks are the sole property of their respective companies.

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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