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WSF512K32-29H2C

Description
Memory Circuit, 512KX32, CMOS, CHMA66, 1.385 INCH SQUARE, HERMETIC SEALED, CERAMIC, HIP-66
Categorystorage    storage   
File Size237KB,14 Pages
ManufacturerWhite Microelectronics
Download Datasheet Parametric View All

WSF512K32-29H2C Overview

Memory Circuit, 512KX32, CMOS, CHMA66, 1.385 INCH SQUARE, HERMETIC SEALED, CERAMIC, HIP-66

WSF512K32-29H2C Parametric

Parameter NameAttribute value
MakerWhite Microelectronics
package instruction1.385 INCH SQUARE, HERMETIC SEALED, CERAMIC, HIP-66
Reach Compliance Codeunknown
JESD-30 codeS-CHMA-P66
memory density16777216 bit
Memory IC TypeMEMORY CIRCUIT
memory width32
Number of functions1
Number of terminals66
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX32
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeSQUARE
Package formMICROELECTRONIC ASSEMBLY
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formPIN/PEG
Terminal locationHEX
White Electronic Designs
512K
X
32 SRAM / FLASH MODULE
FEATURES
Access Times of 25ns (SRAM) and 70, 90ns (FLASH)
Packaging
• 66 pin, PGA Type, 1.385" square HIP, Hermetic
Ceramic HIP (Package 402)
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880")
square (Package 509) 4.57mm (0.180") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (Fig. 2). Package to be developed.
512Kx32 SRAM
512Kx32 5V Flash
Organized as 512Kx32 of SRAM and 512Kx32 of
Flash Memory with common Data Bus
Low Power CMOS
Commercial, Industrial and Military Temperature Ranges
TTL Compatible Inputs and Outputs
PRELIMINARY*
WSF512K32-XXX
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight - 13 grams typical
FLASH MEMORY FEATURES
100,000 Erase/Program Cycles
Sector Architecture
• 8 equal size sectors of 64KBytes each
• Any combination of sectors can be concurrently
erased. Also supports full chip erase
5 Volt Programming; 5V ± 10% Supply
Embedded Erase and Program Algorithms
Hardware Write Protection
Page Program Operation and Internal Program
Control Time.
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note: Programming information available upon request.
FIG. 1
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
11
22
12
PIN CONFIGURATION FOR WSF512K32-29H2X
T
OP
V
IEW
23
FWE
2
SWE
2
GND
I/O
11
A
10
A
9
A
15
V
CC
FCS
SCS
I/O
3
33
I/O
15
I/O
14
I/O
13
I/O
12
OE
A
17
FWE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
SWE
1
A
13
A
8
I/O
16
I/O
17
I/O
18
44
34
V
CC
SWE
4
FWE
4
I/O
27
A
4
A
5
A
6
FWE
3
SWE
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
66
OE
A0-18
SCS
FCS
P
IN
D
ESCRIPTION
I/O
0-31
A
0-18
SWE
1-4
SCS
OE
V
CC
GND
NC
FWE
1-4
FCS
Data Inputs/Outputs
Address Inputs
SRAM Write Enables
SRAM Chip Select
Output Enable
Power Supply
Ground
Not Connected
Flash Write Enables
Flash Chip Select
56
B
LOCK
D
IAGRAM
FWE
1
SWE
1
FWE
2
SWE
2
FWE
3
SWE
3
FWE
4
SWE
4
512K x 8 Flash
512K x 8 SRAM
512K x 8 Flash
512K x 8 SRAM
512K x 8 Flash
512K x 8 SRAM
512K x 8 Flash
512K x 8 SRAM
I/O0-7
I/O8-15
I/O16-23
I/O24-31
October 2002 Rev. 7
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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