Edition 2000-09-14
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 9/14/00.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
PEB 20525
Revision History:
Previous Version:
Page
(previous
Version)
33-35
81
n.a.
n.a.
222
Page
(current
Version)
36-38
84
232, 235
232
226
2000-09-14
PASSAT V1.1 Preliminary Data Sheet, 09.99, DS2
Subjects (major changes since last revision)
DS 1
Correction: signal ’OSR’ is multiplexed with signal ’CD’, signal
’OST’ is multiplexed with ’CTS’ (was vice versa)
corrected HDLC receive address recognition table
Added timing diagram for external DMA support signals
Added address timing diagram for Intel multiplexed mode
(signal ALE)
Chapter "Electrical Characteristics" updated with final
characterization results.
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at
http://www.infineon.com
PEB 20525
PEF 20525
Table of Contents
1
1.1
1.2
1.3
1.3.1
1.3.2
1.4
1.4.1
1.4.2
2
2.1
2.2
2.3
3
3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.3
3.2.3.1
3.2.3.2
3.2.3.3
3.2.3.4
3.2.3.5
3.2.3.6
3.2.3.7
3.2.3.8
3.2.3.9
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
Page
16
17
20
21
21
23
25
25
25
26
26
27
28
42
42
43
43
43
43
44
46
47
51
52
53
54
55
56
63
66
67
68
68
71
72
72
72
73
74
74
74
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Integration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differences between SEROCCO-H and the HSCX/ESCC Family . . . . . .
Enhancements to the HSCX Serial Core . . . . . . . . . . . . . . . . . . . . . . . .
Simplifications to the HSCX Serial Core . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram P-LFBGA-80-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram P-TQFP-100-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Communication Controller (SCC) . . . . . . . . . . . . . . . . . . . . . . . . . .
Protocol Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCC FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCC FIFO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode 0 (0a/0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode 2 (2a/2b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode 3 (3a/3b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode 5a (Time Slot Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode 5b (Octet Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode 6 (6a/6b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Mode 7 (7a/7b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Generator (BRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Recovery (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCC Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCC Serial Bus Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Bus Access Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Bus Collisions and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Bus Access Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Bus Configuration Timing Modes . . . . . . . . . . . . . . . . . . . . . . . .
Functions Of Signal RTS in HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . .
Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Data Sheet
2000-09-14
NXP MCU
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