MC68HC08KH12/H
REV. 1.0
68HC08KH12
68HC708KH12
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June 7, 1999
Semiconductor Products Sector
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Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
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MC68HC(7)08KH12
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List of Sections
Section 1. General Description .......................................23
Section 2. Memory Map ...................................................33
Section 3. Random-Access Memory (RAM) ...................45
Section 4. Read-Only Memory (ROM) .............................47
Section 5. Configuration Register (CONFIG) .................49
Section 6. Central Processor Unit (CPU) .......................51
Section 7. System Integration Module (SIM) .................61
Section 8. Clock Generator Module (CGM) ....................87
Section 9. Universal Serial Bus Module (USB) ............113
Section 10. Monitor ROM (MON) ...................................149
Section 11. Timer Interface Module (TIM) ....................161
Section 12. I/O Ports ......................................................183
Section 13. Computer Operating Properly (COP) .......207
Section 14. External Interrupt (IRQ) .............................213
Section 15. Keyboard Interrupt Module (KBI) ..............219
Section 16. Break Module (BREAK) .............................241
Section 17. Preliminary Electrical Specifications .......247
Section 18. Mechanical Specifications ........................259
MC68HC(7)08KH12
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MOTOROLA
List of Sections
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List of Sections
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MC68HC(7)08KH12
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List of Sections
MOTOROLA
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Table of Contents
General Description
1.1
1.2
1.3
1.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.1
Quad Flat Pack (QFP) Package . . . . . . . . . . . . . . . . . . . . . 28
1.5.2
Power Supply Pins
(V
DDA
, V
SSA
, V
DD1
, V
SS1
, V
DD2
, and V
SS2
) . . . . . . . . . . 29
1.5.3
Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . 30
1.5.4
External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.5
External Interrupt Pin (IRQ1/V
PP
) . . . . . . . . . . . . . . . . . . . . 30
1.5.6
USB Data Pins
(DPLUS0–DPLUS4 and DMINUS0–DMINUS4). . . . . . . 30
1.5.7
Voltage Regulator Out (REGOUT) . . . . . . . . . . . . . . . . . . . 30
1.5.8
Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . . 31
1.5.9
Port B I/O Pins (PTB7–PTB0) . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.10
Port C I/O Pins (PTC4–PTC0). . . . . . . . . . . . . . . . . . . . . . . 31
1.5.11
Port D I/O Pins (PTD7/KBD7–PTD0/KBD0) . . . . . . . . . . . . 31
1.5.12
Port E I/O Pins (PTE4, PTE3/KBE3, PTE2/KBE2/TCH1,
PTE1/KBE1/TCH0, PTE0/KBE0/TCLK) . . . . . . . . . . . . . 31
1.5.13
Port F I/O Pins (PTF7/KBF7–PTF0/KBF0) . . . . . . . . . . . . . 32
Section 2. Memory Map
2.1
2.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Table of Contents
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