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P8344: DescriptionSDLC Communications Controller; File Size598KB，65 Pages; ManufacturerInnovasic（ADI）; Websitehttp://www.innovasic.com/

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P8344 Overview

SDLC Communications Controller

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IA8044/IA8344

SDLC Communications Controller

Data Sheet

March 30, 2010

IA8044/IA8344

SDLC Communications Controller

Data Sheet

IA211010112-04

UNCONTROLLED WHEN PRINTED OR COPIED

Page 1 of 65

http://www.Innovasic.com

Customer Support:

1-888-824-4184

IA8044/IA8344

SDLC Communications Controller

Data Sheet

March 30, 2010

TABLE OF CONTENTS

List of Figures ..................................................................................................................................6

List of Tables ...................................................................................................................................7

Introduction.............................................................................................................................9

1.1 Features .........................................................................................................................9

1.2 Variants .......................................................................................................................10

Packaging, Pin Descriptions, and Physical Dimensions .......................................................10

2.1 PDIP Package ..............................................................................................................11

2.2 PDIP Physical Dimensions..........................................................................................13

2.3 PLCC Package .............................................................................................................14

2.4 PLCC Physical Dimensions ........................................................................................16

Maximum Ratings and DC Characteristics ..........................................................................17

Functional Description..........................................................................................................17

4.1 Functional Block Diagram ..........................................................................................17

4.2 Input/Output Characteristics .......................................................................................19

4.3 Memory Organization .................................................................................................20

4.3.1 Program Memory ............................................................................................20

4.3.2 External Data Memory ...................................................................................20

4.3.3 Internal Data Memory.....................................................................................20

4.3.4 Bit Addressable Memory ................................................................................22

4.4 Special Function Registers ..........................................................................................23

4.5 Ports .............................................................................................................................24

4.6 Port Registers ..............................................................................................................24

4.6.1 Port 0 (P0) .......................................................................................................24

4.6.2 Port 1 (P1) .......................................................................................................25

4.6.3 Port 2 (P2) .......................................................................................................25

4.6.4 Port 3 (P3) .......................................................................................................25

4.7 Timers/Counters ..........................................................................................................26

4.7.1 Timers 0 and 1 ................................................................................................26

4.7.2 Mode 0 ............................................................................................................26

4.7.3 Mode 1 ............................................................................................................27

4.7.4 Mode 2 ............................................................................................................27

4.7.5 Mode 3 ............................................................................................................27

4.7.6 Timer Mode (TMOD) .....................................................................................27

4.7.7 Timer Control (TCON) ...................................................................................28

4.7.8 Timer 0 High Byte (TH0) ...............................................................................29

4.7.9 Timer 0 Low Byte (TL0) ................................................................................29

4.7.10 Timer 1 High Byte (TH1) ...............................................................................29

4.7.11 Timer 1 Low Byte (TL1) ................................................................................29

4.7.12 Timer/Counter Configuration .........................................................................30

4.8 General CPU Registers ................................................................................................32

IA211010112-04

UNCONTROLLED WHEN PRINTED OR COPIED

Page 3 of 65

http://www.Innovasic.com

Customer Support:

1-888-824-4184

IA8044/IA8344

SDLC Communications Controller

Data Sheet

March 30, 2010

4.8.1 Accumulator (ACC)........................................................................................32

4.8.2 B Register (B) .................................................................................................32

4.8.3 Program Status Word (PSW) ..........................................................................32

4.8.4 Stack Pointer (SP) ...........................................................................................33

4.8.5 Data Pointer (DPTR) ......................................................................................33

4.9 Interrupts .....................................................................................................................34

4.9.1 External Interrupts ..........................................................................................34

4.9.2 Timer 0 and Timer 1 Interrupts ......................................................................34

4.9.3 Serial Interface Unit Interrupt .........................................................................34

4.9.4 Interrupt Priority Level Structure ...................................................................34

4.9.5 Interrupt Handling ..........................................................................................35

4.9.6 Interrupt Priority Register (IP)........................................................................35

4.9.7 Interrupt Enable Register (IE) ........................................................................36

4.10 SIU—Serial Interface Unit ..........................................................................................36

4.10.1 SIU Special Function Registers ......................................................................37

4.10.2 Serial Mode Register (SMD) ..........................................................................37

4.10.3 Status/Command Register (STS) ....................................................................38

4.10.4 Send/Receive Count Register (NSNR) ...........................................................39

4.10.5 Station Address Register (STAD) ..................................................................40

4.10.6 Transmit Buffer Start Address Register (TBS) ..............................................40

4.10.7 Transmit Buffer Length Register (TBL) .........................................................40

4.10.8 Transmit Control Byte Register (TCB) ..........................................................40

4.10.9 Receive Buffer Start Address Register (RBS) ................................................41

4.10.10 Receive Buffer Length Register (RBL) ..........................................................41

4.10.11 Receive Field Length Register (RFL) .............................................................41

4.10.12 Receive Control Byte Register (RCB) ............................................................41

4.10.13 DMA Count Register (DMA CNT) ................................................................42

4.10.14 DMA Count Register (FIFO)..........................................................................42

4.10.15 SIU State Counter (SIUST) ............................................................................42

4.11 Data Clocking Options ................................................................................................43

4.12 Operational Modes ......................................................................................................43

4.13 Frame Format Options ................................................................................................44

4.14 HDLC Restrictions ......................................................................................................46

4.15 SIU Details ..................................................................................................................46

4.15.1 BIP ..................................................................................................................46

4.15.2 BYP.................................................................................................................48

4.16 Diagnostics ..................................................................................................................48

AC Specifications .................................................................................................................50

5.1 Memory Access Waveforms .......................................................................................51

5.2 Serial I/O Waveforms ..................................................................................................55

IA211010112-04

UNCONTROLLED WHEN PRINTED OR COPIED

Page 4 of 65

http://www.Innovasic.com

Customer Support:

1-888-824-4184

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