TSPC750ACCIP266CE datasheet, PDF

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TSPC750ACCIP266CE: DescriptionRISC Microprocessor, 32-Bit, 266MHz, CMOS, 2.54 MM PITCH, PCM, PGA-288; CategoryThe embedded processor and controller Microcontrollers and processors; File Size210KB，17 Pages; ManufacturerAtmel (Microchip)

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TSPC750ACCIP266CE Overview

RISC Microprocessor, 32-Bit, 266MHz, CMOS, 2.54 MM PITCH, PCM, PGA-288

TSPC750ACCIP266CE Parametric

Parameter Name	Attribute value
Maker	Atmel (Microchip)
Parts packaging code	PGA
package instruction	,
Contacts	288
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Address bus width	32
bit size	32
boundary scan	YES
External data bus width	64
Integrated cache	YES
JESD-30 code	R-XXMA-P288
Number of terminals	288
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
speed	266 MHz
Maximum supply voltage	2.73 V
Minimum supply voltage	2.47 V
Nominal supply voltage	2.6 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	PIN/PEG
Terminal location	UNSPECIFIED
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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TSPC750IP

Processor and Cache Module

DESCRIPTION

The Processor and Cache Module (PCM) is a 17 x 17 pin grid

array (PGA) circuit assembly which combines a PowerPCt

microprocessor and SRAM components into a CPU subsys-

tem. The PCM provides a standard mechanical, electrical, and

functional interface which can be socketed on a computer sys-

tem board and allows many combinations of processors and

optional components to be easily interchanged. This docu-

ment describes the general characteristics for a module con-

sisting of a single PowerPCt microprocessor and two SRAM

devices for L2 cache. The PCM packaging and PGA signal

definition also accomodates single processors without SRAM,

and multiple processors.

The PCM consists of an epoxy–glass (FR4) substrate which

adapts a processor in a ceramic ball grid array (CBGA) pac-

kage with 50 mil spacing to a 288–pin PGA with 100 mil spac-

ing that can be easily socketed and hence, easily upgraded.

The FR4 substrate can be extended beyond the area of the 17

x 17 pin grid array to provide an interconnect area for SRAM

components configured as closely coupled L2 cache. The

resulting PCM provides numerous flexible configurations of

processor and cache for various price/performance system

designs.

FR4 PCM on PGA 288 Interposer

60x Address

60x Data

60x Control

PLL_CFG

TSPC750

Processor

L2 Addr

L2 Data

L2 Control

L2–Cache

Memory

Chips

VID

PID

General

Support

Circuits

Simplified Block Diagram

April 1999

1/17

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