CMDP-67201AL-20 datasheet, PDF

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CMDP-67201AL-20: DescriptionFIFO, 512X9, 20ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28; Categorystorage storage; File Size181KB，17 Pages; ManufacturerTEMIC; Websitehttp://www.temic.de/

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CMDP-67201AL-20 Overview

FIFO, 512X9, 20ns, Asynchronous, CMOS, CDFP28, 0.400 INCH, FP-28

CMDP-67201AL-20 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	TEMIC
package instruction	0.400 INCH, FP-28
Reach Compliance Code	unknown
Maximum access time	20 ns
Maximum clock frequency (fCLK)	33.33 MHz
period time	30 ns
JESD-30 code	R-CDFP-F28
JESD-609 code	e0
memory density	4608 bit
Memory IC Type	OTHER FIFO
memory width	9
Number of functions	1
Number of terminals	28
word count	512 words
character code	512
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512X9
Output characteristics	3-STATE
Exportable	NO
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Encapsulate equivalent code	FL28,.4
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Maximum slew rate	0.14 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL

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M67201A/M67202A

512

9 & 1 K

9 CMOS Parallel FIFO

Introduction

The M67201A/202A implement a first-in first-out

algorithm, featuring asynchronous read/write operations.

The FULL and EMPTY flags prevent data overflow and

underflow. The Expansion logic allows unlimited

expansion in word size and depth with no timing

penalties. Twin address pointers automatically generate

internal read and write addresses, and no external address

information are required for the TEMIC FIFOs. Address

pointers are automatically incremented with the write pin

and read pin. The 9 bits wide data are used in data

communications applications where a parity bit for error

checking is necessary. The Retransmit pin reset the Read

pointer to zero without affecting the write pointer. This is

very useful for retransmitting data when an error is

detected in the system.

Using an array of eigh transistors (8 T) memory cell and

fabricated with the state of the art 1.0

µm

lithography

named SCMOS, the M 67201A/202A combine an

extremely low standby supply current (typ = 1.0

µA)

with

a fast access time at 25 ns over the full temperature range.

All versions offer battery backup data retention capability

with a typical power consumption at less than 5

µW.

For military/space applications that demand superior

levels

performance

and

reliability

the

M 67201A/202A is processed according to the methods

of the latest revision of the MIL STD 883 (class B or S)

and/or ESA SCC 9000.

Features

First-in first-out dual port memory

512

9 organisation (M 67201A)

1024

9 organisation (M 67202A)

Fast access time

20*, 25, 35, 45, 55 ns, commercial, industrial and

automotive

20*, 25, 30, 40, 50 ns, military

Wide temperature range :

– 55°C to + 125°C

67201AL/202AL low power 67201AV/202AV very low

power

Fully expandable by word width or depth

* Preview. Please Consult Sales.

Asynchronous read/write operations

Empty, full and half flags in single device mode

Retransmit capability

Bi-directional applications

Battery back-up operation : 2 V data retention

TTL compatible

Single 5 V

10 % Power Supply (1)

High performance SCMOS technology

(1) 3.3 V versions are also available. Please consult sales.

MATRA MHS

Rev. D (11 April. 97)

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