K6F2008V2M, K6F2008S2M, K6F2008R2M Family
Document Title
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
CMOS SRAM
Revision History
Revision No. History
0.0
0.1
Initial draft
Revise
- Remove sTSOP1 from product
- Rename high power product to low power.
I
SB1
=10.0mA(Max)
- Add super low power version with special handling
I
SB1
=1.0mA(Max)
- Remove 70ns and add 85ns part on KM68F2000 Family
Finalize
Revise
- Change datasheet format
- Remove reverse type package from product
- Remove reseved speed bin(100ns)
Draft Date
October 2, 1996
December 1, 1996
Remark
Advance
Preliminary
1.0
2.0
April 11, 1997
March 5, 1998
Final
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0
March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
FEATURES
• Process Technology: Full CMOS
• Organization: 256Kx8
• Power Supply Voltage
K6F2008V2M Family: 3.0 ~ 3.6V
K6F2008S2M Family: 2.3 ~ 3.3V
K6F2008R2M Family: 1.8 ~ 2.7V
• Low Data Retention Voltage: 1.5V(Min)
• Three state output and TTL Compatible
• Package Type: 32-TSOP1-0820F
CMOS SRAM
GENERAL DESCRIPTION
The K6F2008V2M, K6F2008S2M and K6F2008R2M families
are fabricated by SAMSUNG′s advanced Full CMOS process
technology. The families support various operating temperature
ranges and have various package types for user flexibility of
system design. The families also supports low data retention
voltage for battery back-up operation with low data retention
current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed(ns)
Standby
(I
SB1
, Max)
Operating
(I
CC2
, Max)
60mA
55mA
30mA
10µA
2)
15mA
60mA
55mA
30mA
15mA
32-TSOP1-F
PKG Type
K6F2008V2M-C
K6F2008S2M-C
K6F2008R2M-C
K6F2008V2M-I
K6F2008S2M-I
K6F2008R2M-I
Industrial(-40~85°C)
Commercial(0~70°C)
3.0~3.6V
2.3~3.3V
1.8~2.7V
3.0~3.6V
2.3~3.3V
1.8~2.7V
70
1)
/85@V
CC
=3.3±0.3V
85@V
CC
=3.0±0.3V
120
1)
/150@V
CC
=2.5±0.2V
300
1)
@V
CC
=2.0±0.2V
70
1)
/85@V
CC
=3.3±0.3V
85@V
CC
=3.0±0.3V
120
1)
/150@V
CC
=2.5±0.2V
300
1)
@V
CC
=2.0±0.2V
1. The parameter is measured with 30pF test load.
2. 2µA for super low power version with special handling.
PIN DESCRIPTION
A11
A9
A8
A13
WE
CS2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
A14
A12
A7
A6
A5
A4
A2
A3
A0
A1
32-TSOP
Type I - Forward
Row
select
Memory array
1024 rows
256¥8 columns
Name
Function
Name
Function
I/O
1
I/O
8
CS
1
,CS
2
Chip Select Input
OE
WE
Output Enable
Write Enable Input
I/O
1
~I/O
8
Data Inputs/Outputs
Vcc
Vss
N.C.
Power
Ground
No Connection
Data
cont
I/O Circuit
Column select
A
0
~A
17
Address Inputs
Data
cont
A9 A11 A10 A15 A13 A8 A16 A17
CS1
CS2
WE
OE
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 2.0
March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
K6F2008V2M-TC70
K6F2008V2M-TC85
K6F2008S2M-TC12
K6F2008S2M-TC15
K6F2008R2M-TC30
Function
32-TSOP F, 70ns, 3.3V, LL
32-TSOP F, 85ns, 3.3V, LL
32-TSOP F, 120/85ns, 2.5/3.0V, LL
32-TSOP F, 150/85ns, 2.5/3.0V, LL
32-TSOP F, 300ns, 2.0/2.5V, LL
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
K6F2008V2M-TI70
K6F2008V2M-TI85
K6F2008S2M-TI12
K6F2008S2M-TI15
K6F2008R2M-TI30
Function
32-TSOP F, 70ns, 3.3V, LL
32-TSOP F, 85ns, 3.3V, LL
32-TSOP F, 120/85ns, 2.5/3.0V, LL
32-TSOP F, 150/85ns, 2.5/3.0V, LL
32-TSOP F, 300ns, 2.0/2.5V, LL
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disable
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don
′
t care (Must be high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Soldering temperature and time
Symbol
V
IN
,V
OU
V
CC
P
D
T
STG
T
A
-40 to 85
T
SOLDER
260°C, 5sec (Lead Only)
Ratings
-0.2 to 3.6V
2)
-0.2 to 4.0V
3)
1.0
-55 to 150
0 to 70
Unit
V
V
W
°C
°C
°C
-
Remark
-
-
-
-
K6F2008V2M-C, K6F2008S2M-C, K6F2008R2M-C
K6F2008V2M-I, K6F2008S2M-I, K6F2008R2M-I
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V
IN
/V
OUT
=-0.2 to 3.9V for K6F2008V2M Family.
3. Maximum V
CC
=-0.2 to 4.6V for K6F2008V2M Family.
3
Revision 2.0
March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Symbol
Vcc
Vss
Product
K6F2008V2M Family
K6F2008S2M Family
K6F2008R2M Family
All Family
K6F2008V2M Family
K6F2008S2M Family
Vcc=3.3±0.3V
Vcc=3.0±0.3V
Vcc=2.5±0.2V
K6F2008R2M Family
Input low voltage
V
IL
All Family
Vcc=2.5±0.2V
Vcc=2.0±0.2V
Min
3.0
2.3
1.8
0
2.2
2.2
2.0
2.0
1.6
-0.2
3)
-
-
Typ
2)
3.3
2.5/3.0
2.0/2.5
0
CMOS SRAM
Max
3.6
3.3
2.7
0
Unit
V
V
Input high voltage
V
IH
Vcc+0.2
2)
V
0.4
V
Note
1. Commercial Product : T
A
=0 to 70°C, unless otherwise specified
Industrial Product : T
A
=-40 to 85°C, unless otherwise specified
2. Overshoot : Vcc + 1.0V in case of pulse width≤20ns
3. Undershoot : -1.0V in case of pulse width≤20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Cycle time=Min, 100% duty, I
IO
=0mA,
CS1=V
IL
, CS2=V
IH,
V
IN
=V
IL
or V
IH
Test Conditions
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL,
V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IL
or V
IH
, Read
Cycle time=1
µs
, 100% duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥V
CC
-0.2V, V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Min
-1
-1
-
Read
Write
-
-
-
-
-
-
-
-
2.4
2.0
1.6
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
1
1
10
10
15
55
1)
30
15
0.4
0.4
0.4
-
-
-
0.3
10
2)
Unit
mA
mA
mA
mA
Vcc=3.3V@70ns
Vcc=2.7V@120ns
Vcc=2.2V@300ns
2.1mA at Vcc=3.0/3.3V
mA
Output low voltage
V
OL
I
OL
0.5mA at Vcc=2.5V
0.33mA at Vcc=2.0V
-1.0mA at Vcc=3.0/3.3V
V
Output high voltage
V
OH
I
OH
-0.5mA at Vcc=2.5V
-0.44mA at Vcc=2.0V
V
Standby Current(TTL)
Standby Current(CMOS)
I
SB
I
SB1
CS
1
=V
IH
or CS
2
=V
IL,
Other inputs=V
IL
or V
IH
CS
1
≥Vcc-0.2V,
CS2≥Vcc-0.2V or CS
2
≤0.2V,
Other inputs=0~Vcc
mA
µA
1.The value is measured at Vcc=3.0±0.3V
- ICC2=60mA with 70ns at Vcc=3.3±0.3V, but this value is not 100% tested but obtained statistically.
2. Super low power product = 2µA with special handling.
4
Revision 2.0
March 1998
K6F2008V2M, K6F2008S2M, K6F2008R2M Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V for Vcc=3.3V, 3.0V, 2.5V
0.4 to 1.8V for Vcc=2.0V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V for Vcc=3.3V, 3.0V
1.1V for Vcc=2.5V
0.9V for Vcc=2.0V
Output load (See right):C
L
=100pF+1TTL
C
L
=30pF+1TTL
CMOS SRAM
V
TM
3)
R
1
2)
C
L
1)
R
2
3)
1. Including scope and jig capacitance
2. R
1
=3070W
,
R
2
=3150W
3. V
TM
=2.8V for V
CC
=3.0/3.3V
=2.3V for V
CC
=2.5V
=1.8V for V
CC
=2.0V
AC CHARACTERISTICS
(Commercial product:T
A
=0 to 70°C, Industrial product: T
A
=-40 to 85°C
K6F2008V2M Family: Vcc=3.0~3.6V, K6F2008S2M Family: Vcc=2.3~3.3V,
K6F2008R2M Family: Vcc=1.8~2.7V)
Speed Bins
Parameter List
Symbol
70ns
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ1
, t
LZ2
t
OLZ
t
HZ1
, t
HZ2
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
70
-
-
-
10
5
0
0
10
70
65
0
65
55
0
0
30
0
5
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
85ns
Min
85
-
-
-
10
5
0
0
15
85
70
0
70
60
0
0
35
0
5
Max
-
85
85
45
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
120ns
Min
120
-
-
-
10
5
0
0
15
120
100
0
100
80
0
0
50
0
5
Max
-
120
120
60
-
-
35
35
-
-
-
-
-
-
-
35
-
-
-
150ns
Min
150
-
-
-
20
10
0
0
15
150
120
0
120
100
0
0
60
0
5
Max
-
150
150
75
-
-
40
40
-
-
-
-
-
-
-
40
-
-
-
300ns
Min
300
-
-
-
50
30
0
0
30
300
300
0
300
200
0
0
120
0
20
Max
-
300
300
150
-
-
60
60
-
-
-
-
-
-
-
60
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS
1
≥Vcc-0.2V
1)
Vcc=3.0V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Min
1.5
-
0
t
RC
Typ
-
-
-
-
Max
3.6
10
2)
-
-
Unit
V
µA
ns
1. CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or CS
2
≤0.2V(CS
2
controlled)
2. Super low power product = 2µA with special handling.
5
Revision 2.0
March 1998
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