IS66WVE2M16EBLL-70BI datasheet, PDF

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IS66WVE2M16EBLL-70BI: DescriptionPseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, MO-207, TFBGA-48; Categorystorage storage; File Size617KB，31 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS66WVE2M16EBLL-70BI Overview

Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, MO-207, TFBGA-48

IS66WVE2M16EBLL-70BI Parametric

Parameter Name	Attribute value
Maker	Integrated Silicon Solution ( ISSI )
package instruction	TFBGA,
Reach Compliance Code	unknown
Maximum access time	70 ns
JESD-30 code	R-PBGA-B48
length	8 mm
memory density	33554432 bit
Memory IC Type	PSEUDO STATIC RAM
memory width	16
Number of functions	1
Number of terminals	48
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.75 mm
Terminal location	BOTTOM
width	6 mm

IS66WVE2M16EBLL-70BI Preview

IS66WVE2M16EALL/BLL/CLL

IS67WVE2M16EALL/BLL/CLL

32Mb Async/Page PSRAM

ADVANCED INFORMATION

Overview

The IS66/67WVE2M16EALL/BLL/CLL is an integrated memory device containing 32Mbit Pseudo Static

Random Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits. The device

includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of

the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has

separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device

core.

Features



Asynchronous and page mode interface



Dual voltage rails for optional performance



ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V



BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V



CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V



Page mode read access



Interpage Read access : 70ns



Intrapage Read access : 20ns



Low Power Consumption



Asynchronous Operation < 30 mA



Intrapage Read < 18mA



Standby < 180 µA (max.)



Deep power-down (DPD)



ALL/CLL: < 3µA (Typ)



BLL: < 10µA (Typ)



Low Power Feature



Temperature Controlled Refresh



Partial Array Refresh



Deep power-down (DPD) mode



Operating temperature Range

Industrial: -40°C~85°C

Automotive A1: -40°C~85°C



Package:

48-ball TFBGA

products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services

described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information

and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or

effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to

its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Rev. 00A | Jan. 2014

www.issi.com

- SRAM@issi.com

IS66WVE2M16EALL/BLL/CLL

IS67WVE2M16EALL/BLL/CLL

General Description

PSRAM products are high-speed, CMOS pseudo-static random access memory developed

for low-power, portable applications. The 32Mb DRAM core device is organized

as 2 Meg x 16 bits. These devices include the industry-standard, asynchronous memory

interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings.

For seamless operation on an asynchronous memory bus, PSRAM products incorporated a

transparent self-refresh mechanism. The hidden refresh requires no additional support

from the system memory controller and has no significant impact on device read/write

performance.

A user-accessible configuration registers (CR) defines how the PSRAM device performs on-

chip refresh and whether page mode read accesses are permitted. This register is

automatically loaded with a default setting during power-up and can be updated at any

time during normal operation.

Special attention has been focused on current consumption during self-refresh. This

product includes two system-accessible mechanisms to minimize refresh current.

Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array

refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the

DRAM array that contains essential data. DPD halts refresh operation altogether and is

used when no vital information is stored in the device. The system-configurable refresh

mechanisms are accessed through the CR.

A0~A20

Address

Decode Logic

2M X 16

DRAM

Memory Array

Input

/Output

Mux

And

Buffers

Configuration Register

(CR)

CE#

WE#

OE#

LB#

UB#

ZZ#

Control

Logic

DQ0~DQ15

[ Functional Block Diagram]

Rev. 00A | Jan. 2014

www.issi.com

- SRAM@issi.com

IS66WVE2M16EALL/BLL/CLL

IS67WVE2M16EALL/BLL/CLL

48Ball TFBGA Ball Assignment

LB#

DQ8

DQ9

VSSQ

VDDQ

DQ14

DQ15

A18

OE#

UB#

DQ10

DQ11

DQ12

DQ13

A19

A17

A14

A12

A16

A15

A13

A10

CE#

DQ1

DQ3

DQ4

DQ5

WE#

A11

ZZ#

DQ0

DQ2

VDD

VSS

DQ6

DQ7

A20

[Top View]

(Ball Down)

Rev. 00A | Jan. 2014

www.issi.com

- SRAM@issi.com

IS66WVE2M16EALL/BLL/CLL

IS67WVE2M16EALL/BLL/CLL

Signal Descriptions

All signals for the device are listed below in Table 1.

Table 1. Signal Descriptions

Symbol

VSS

VSSQ

DQ0~DQ15

A0~A20

LB#

UB#

CE#

OE#

WE#

ZZ#

Type

Power Supply

Input / Output

Input

Description

All VSS supply pins must be connected to Ground

All VSSQ supply pins must be connected to Ground

Data Inputs/Outputs (DQ0~DQ15)

Address Input(A0~A20)

Lower Byte select

Upper Byte select

Chip Enable/Select

Output Enable

Write Enable

Sleep enable : When ZZ# is LOW, the CR can be loaded, or the device

can enter one of two low-power modes ( DPD or PAR).



ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V



BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V



CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V

Rev. 00A | Jan. 2014

www.issi.com

- SRAM@issi.com

IS66WVE2M16EALL/BLL/CLL

IS67WVE2M16EALL/BLL/CLL

Functional Description

All functions for the device are listed below in Table 2.

Table 2. Functional Descriptions

Mode

Standby

Read

Write

No operation

PAR

DPD

Load

Configuration

Power

Standby

Active

Idle

PAR

DPD

Active

CE#

WE#

OE#

UB#/LB#

ZZ#

[15:0]

High-Z

Data-Out

Data-In

High-Z

Note

2,5

1,4

1,3,4

4,5

Notes

1. When UB# and LB# are in select mode (LOW), DQ0~DQ15 are affected as shown.

When only LB# is in select mode, DQ0~DQ7 are affected as shown. When only UB# is

in select mode, DQ8~DQ15 are affected as shown.

2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data

inputs/outputs are internally isolated from any external influence.

3. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os.

4. The device will consume active power in this mode whenever addresses are changed.

5. Vin=VDDQ or 0V, all device pins be static (unswitched) in order to achieve standby current.

6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.

Rev. 00A | Jan. 2014

www.issi.com

- SRAM@issi.com

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IS66WVE2M16EBLL-70BI Related Products

	IS66WVE2M16EBLL-70BI	IS66WVE2M16EALL-70BI
Description	Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, MO-207, TFBGA-48	Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, MO-207, TFBGA-48
Maker	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
package instruction	TFBGA,	6 X 8 MM, MO-207, TFBGA-48
Reach Compliance Code	unknown	unknown
Maximum access time	70 ns	70 ns
JESD-30 code	R-PBGA-B48	R-PBGA-B48
length	8 mm	8 mm
memory density	33554432 bit	33554432 bit
Memory IC Type	PSEUDO STATIC RAM	PSEUDO STATIC RAM
memory width	16	16
Number of functions	1	1
Number of terminals	48	48
word count	2097152 words	2097152 words
character code	2000000	2000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
organize	2MX16	2MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	1.95 V
Minimum supply voltage (Vsup)	2.7 V	1.7 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL
Terminal pitch	0.75 mm	0.75 mm
Terminal location	BOTTOM	BOTTOM
width	6 mm	6 mm

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