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MC74LVX8053
Analog Multiplexer /
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVX8053 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from VCC to GND).
The LVX8053 is similar in pinout to the high−speed HC4053A, and
the metal−gate MC14053B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pull−up resistors they are compatible with
LSTTL outputs.
This device has been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal−gate CMOS analog
switches.
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16−LEAD SOIC
D SUFFIX
CASE 751B
16−LEAD TSSOP
DT SUFFIX
CASE 948F
PIN CONNECTION AND
MARKING DIAGRAM
(Top View)
VCC
16
Y
15
X
14
X1
13
X0
12
A
11
B
10
C
9
•
•
•
•
•
•
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (VCC − GND) = 2.0 to 6.0 V
Digital (Control) Power Supply Range (VCC − GND) = 2.0 to 6.0 V
Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
•
Low Noise
•
In Compliance With the Requirements of JEDEC Standard No. 7A
•
Chip Complexity: LVX8053 — 156 FETs or 39 Equivalent Gates
LOGIC DIAGRAM
Triple Single−Pole, Double−Position Plus Common Off
X0
13
X1
Y0
1
Y1
Z0
3
Z1
CHANNEL-SELECT
INPUTS
A
10
B
9
C
6
ENABLE
11
5
2
12
1
Y1
2
Y0
3
Z1
4
Z
5
Z0
6
Enable
7
NC
8
GND
For detailed package marking information, see the Marking
Diagram section on page 161 of this data sheet.
FUNCTION TABLE − MC74LVX8053
Control Inputs
Enable
L
L
L
L
L
L
L
L
H
X = Don’t Care
C
L
L
L
L
H
H
H
H
X
Select
B
A
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
ON Channels
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
X1
X0
X1
X0
X1
X0
X1
X SWITCH
14
X
ANALOG
INPUTS/OUTPUTS
Y SWITCH
15
Y
COMMON
OUTPUTS/INPUTS
Z SWITCH
4
Z
ORDERING INFORMATION
Device
MC74LVX8053D
MC74LVX8053DR2
MC74LVX8053DT
MC74LVX8053DTR2
Package
SOIC
SOIC
TSSOP
TSSOP
Shipping
48 Units/Rail
2500 Units/Reel
96 Units/Rail
2500 Units/Reel
PIN 16 = VCC
PIN 8 = GND
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls
the Y−Switch and Input C controls the Z−Switch
©
Semiconductor Components Industries, LLC, 2000
151
March, 2000 − Rev. 2
Publication Order Number:
MC74LVX8053/D
MC74LVX8053
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MAXIMUM RATINGS*
Symbol
VCC
VIS
Vin
I
Parameter
Value
Unit
V
V
V
Positive DC Supply Voltage
Analog Input Voltage
(Referenced to GND)
– 0.5 to + 7.0
− 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
±
20
500
450
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
Power Dissipation in Still Air,
Storage Temperature Range
mA
PD
SOIC Package†
TSSOP Package†
mW
_C
_C
Tstg
– 65 to + 150
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
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Symbol
VCC
VIS
Vin
Parameter
Min
2.0
0.0
Max
6.0
Unit
V
V
V
V
Positive DC Supply Voltage
Analog Input Voltage
(Referenced to GND)
VCC
VCC
1.2
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
GND
VIO*
TA
Operating Temperature Range, All Package Types
– 55
+ 85
_C
Input Rise/Fall Time
ns/V
(Channel Select or Enable Inputs)
0
100
VCC = 3.3 V
±
0.3 V
0
20
VCC = 5.0 V
±
0.5 V
*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.
tr, tf
RECOMMENDED OPERATING CONDITIONS
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152
MC74LVX8053
DC CHARACTERISTICS — Digital Section
(Voltages Referenced to GND)
VCC
V
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
5.5
5.5
Guaranteed Limit
−55 to 25°C
1.50
2.10
3.15
3.85
0.5
0.9
1.35
1.65
±
0.1
4
≤85°C
1.50
2.10
3.15
3.85
0.5
0.9
1.35
1.65
±
1.0
40
≤125°C
1.50
2.10
3.15
3.85
0.5
0.9
1.35
1.65
±
1.0
160
Unit
V
Symbol
VIH
Parameter
Minimum High−Level Input
Voltage, Channel−Select or
Enable Inputs
Maximum Low−Level Input
Voltage, Channel−Select or
Enable Inputs
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
Maximum Quiescent Supply
Current (per Package)
Condition
Ron = Per Spec
VIL
Ron = Per Spec
V
Iin
ICC
Vin = VCC or GND,
Channel Select, Enable and
VIS = VCC or GND; VIO = 0 V
µA
µA
DC ELECTRICAL CHARACTERISTICS
Analog Section
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Guaranteed Limit
v
85_C
45
32
28
35
28
25
20
12
12
Symbol
Ron
Parameter
Test Conditions
VCC
V
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
5.5
– 55 to
25_C
40
30
25
30
25
20
v
125_C
50
37
30
40
35
30
25
15
15
Unit
Ω
Maximum “ON” Resistance
Vin = VIL or VIH
VIS = VCC to GND
|IS|
v
10.0 mA (Figures 1, 2)
∆R
on
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Ioff
Maximum Off−Channel Leakage
Current, Any One Channel
Maximum Off−Channel
Leakage Current,
Common Channel
Maximum On−Channel
Leakage Current,
Channel−to−Channel
Vin = VIL or VIH
VIS = VCC or GND (Endpoints)
|IS|
v
10.0 mA (Figures 1, 2)
Vin = VIL or VIH
VIS = 1/2 (VCC − GND)
|IS|
v
10.0 mA
Vin = VIL or VIH;
VIO = VCC or GND;
Switch Off (Figure 3)
Vin = VIL or VIH;
VIO = VCC or GND;
Switch Off (Figure 4)
15
8.0
8.0
Ω
0.1
0.5
1.0
µA
5.5
0.1
1.0
2.0
Ion
Vin = VIL or VIH;
Switch−to−Switch =
VCC or GND; (Figure 5)
5.5
0.1
1.0
2.0
µA
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153
MC74LVX8053
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 3 ns)
Symbol
tPLH,
tPHL
Parameter
Maximum Propagation Delay, Channel−Select to Analog Output
(Figure 9)
VCC
V
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
Guaranteed Limit
−55 to 25°C
30
20
15
15
4.0
3.0
1.0
1.0
30
20
15
15
20
12
8.0
8.0
10
35
50
1.0
≤85°C
35
25
18
18
6.0
5.0
2.0
2.0
35
25
18
18
25
14
10
10
10
35
50
1.0
≤125°C
40
30
22
20
8.0
6.0
2.0
2.0
40
30
22
20
30
15
12
12
10
35
50
1.0
pF
Unit
ns
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
ns
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
ns
Cin
CI/O
Maximum Input Capacitance, Channel−Select or Enable Inputs
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I
Feedthrough
pF
pF
CPD
Power Dissipation Capacitance (Figure 13)*
Typical @ 25°C, VCC = 5.0 V
45
* Used to determine the no−load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC .
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