Freescale Semiconductor
Technical Data
MPC9446
Rev. 3, 08/2005
2.5 V and 3.3 V LVCMOS Clock
Fanout Buffer
The MPC9446 is a 2.5 V and 3.3 V compatible 1:10 clock distribution buffer
designed for low-voltage mid-range to high-performance telecom, networking
and computing applications. Both 3.3 V, 2.5 V and dual supply voltages are
supported for mixed-voltage applications. The MPC9446 offers 10 low-skew
outputs and 2 selectable inputs for clock redundancy. The outputs are
configurable and support 1:1 and 1:2 output to input frequency ratios. The
MPC9446 is specified for the extended temperature range of –40°C to 85°C.
Features
•
•
•
•
•
•
•
•
•
•
•
Configurable 10 outputs LVCMOS clock distribution buffer
Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply
Wide range output clock frequency up to 250 MHz
Designed for mid-range to high-performance telecom, networking
and computer applications
Supports applications requiring clock redundancy
Maximum output skew of 200 ps (150 ps within one bank)
Selectable output configurations per output bank
Tristable outputs
32-lead LQFP package
32-lead Pb-free package available
Ambient operating temperature range of –40 to 85°C
MPC9446
LOW VOLTAGE SINGLE OR
DUAL SUPPLY 2.5 V AND 3.3 V
LVCMOS CLOCK
DISTRIBUTION BUFFER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Functional Description
The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250 MHz. The signals are generated and
retimed on-chip to ensure minimal skew between the three output banks. Two independent LVCMOS compatible clock inputs are
available. This feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three
output banks can be individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx pins choose be-
tween division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three
output banks. The MPC9446 can be rese,t and the outputs are disabled by deasserting the MR/OE pin (logic high state). Assert-
ing MR/OE will enable the outputs.
All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated
50
Ω
transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible in-
puts. For series terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an
effective fanout of 1:20. The device is packaged in a 7x7 mm
2
32-lead LQFP package.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
CCLK0
CCLK1
CCLK_SEL
V
CC
25k
V
CC
25k
Bank A
0
1
CLK
CLK
÷
2
0
1
QA0
QA1
QA2
25k
0
1
Bank B
QB0
QB1
QB2
QC0
QC1
QC2
QC3
FSELA
FSELB
FSELC
MR/OE
Bank C
25k
25k
25k
25k
0
1
Figure 1. MPC9446 Logic Diagram
V
CCC
V
CCB
V
CCB
GND
GND
QB0
QB1
QB2
V
CCB
is internally connected to V
CC
24
V
CCA
QA2
GND
QA1
V
CCA
QA0
GND
MR/OE
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
23
22
21
20
19
18
17
16
15
14
QC3
GND
QC2
V
CCC
QC1
GND
QC0
V
CCC
MPC9446
13
12
11
10
9
FSELA
FSELB
FSELC
CCLK_SEL
CCLK0
Figure 2. Pinout: 32-Lead Package Pinout
(Top View)
MPC9446
2
Advanced Clock Drivers Devices
Freescale Semiconductor
CCLK1
GND
V
CC
Table 1. Pin Configuration
Pin
CCLK0,1
FSELA, FSELB, FSELC
MR/OE
GND
V
CCA
, V
CCB(1)
, V
CCC
V
CC
QA0 – QA2
QB0 – QB2
QC0 – QC3
Output
Output
Output
Input
Input
Input
I/O
Type
LVCMOS
LVCMOS
LVCMOS
Supply
Supply
Supply
LVCMOS
LVCMOS
LVCMOS
LVCMOS clock inputs
Output bank divide select input
Internal reset and output (high impedance) control
Negative voltage supply (GND)
Positive voltage supply for output banks
Positive voltage supply for core (VCC)
Bank A outputs
Bank B outputs
Bank C outputs
Function
1. V
CCB
is internally connected to V
CC
.
Table 2. Supported Single and Dual Supply Configurations
Supply Voltage Configuration
3.3 V
Mixed Voltage Supply
2.5 V
1.
2.
3.
4.
V
CC(1)
3.3 V
3.3 V
2.5 V
V
CCA(2)
3.3 V
3.3 V or 2.5 V
2.5 V
V
CCB(3)
3.3 V
3.3 V
2.5 V
V
CCC(4)
3.3 V
3.3 V or 2.5 V
2.5 V
GND
0V
0V
0V
V
CC
is the positive power supply of the device core and input circuitry. V
CC
voltage defines the input threshold and levels.
V
CCA
is the positive power supply of the bank A outputs. V
CCA
voltage defines bank A output levels.
V
CCB
is the positive power supply of the bank B outputs. V
CCB
voltage defines bank B output levels. V
CCB
is internally connected to V
CC
.
V
CCC
is the positive power supply of the bank C outputs. V
CCC
voltage defines bank C output levels.
Table 3. Function Table (Controls)
Control
CCLK_SEL
FSELA
FSELB
FSELC
MR/OE
Default
0
0
0
0
0
CCLK0
f
QA0:2
= f
REF
f
QB0:2
= f
REF
f
QC0:3
= f
REF
Outputs enabled
0
CCLK1
f
QA0:2
= f
REF
÷
2
f
QB0:2
= f
REF
÷
2
f
QC0:3
= f
REF
÷
2
Internal reset outputs disabled (tristate)
1
Table 4. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.6
V
CC
+0.3
V
CC
+0.3
±20
±50
125
Unit
V
V
V
mA
mA
°C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
MPC9446
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 5. General Specifications
Symbol
V
TT
MM
HBM
LU
C
PD
C
IN
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Power Dissipation Capacitance
Input Capacitance
200
2000
200
10
4.0
Min
Typ
V
CC
÷
2
Max
Unit
V
V
V
mA
pF
pF
Per output
Condition
Table 6. DC Characteristics
(V
CC
= V
CCA
= V
CCB
= V
CCC
= 3.3 V ± 5%, T
A
= –40°C to +85°C)
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
Z
OUT
I
CCQ(3)
Characteristics
Input High Voltage
Input Low Voltage
Input Current
(1)
Output High Voltage
Output Low Voltage
Output Impedance
Maximum Quiescent Supply Current
14 – 17
2.0
2.4
0.55
0.30
Min
2.0
–0.3
Typ
Max
V
CC
+ 0.3
0.8
200
Unit
V
V
µA
V
V
V
Ω
mA
All V
CC
Pins
Condition
LVCMOS
LVCMOS
V
IN
= GND or V
IN
= VCC
I
OH
= –24 mA
(2)
I
OL
= 24 mA
(2)
I
OL
= 12 mA
1. Input pull-up / pull-down resistors influence input current.
2. The MPC9446 is capable of driving 50
Ω
transmission lines on the incident edge. Each output drives one 50
Ω
parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
Ω
series terminated transmission lines.
3. I
CCQ
is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 7. AC Characteristics
(V
CC
= V
CCA
= V
CCB
= V
CCC
= 3.3 V ± 5%, T
A
= –40°C to +85°C)
(1)
Symbol
f
ref
f
MAX
t
P, REF
t
r
, t
f
t
PLH
t
PHL
t
PLZ, HZ
t
PZL, LZ
t
sk(O)
Input Frequency
Maximum Output Frequency
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation Delay
Output Disable Time
Output Enable Time
Output-to-Output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
Device-to-Device Skew
Output Pulse Skew
(4)
Output Duty Cycle
Output Rise/Fall Time
÷1
output
÷2
output
47
45
0.1
50
50
CCLK0,1 to any Q
CCLK0,1 to any Q
2.2
2.2
2.8
2.8
÷1
output
÷2
output
Characteristics
Min
0
0
0
1.4
1.0
(3)
4.45
4.2
10
10
150
200
350
2.25
200
53
55
1.0
Typ
Max
250
(2)
250
(2)
125
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns
ps
%
%
ns
DC
REF
= 50%
DC
REF
= 25%–75%
0.55 to 2.4 V
0.8 to 2.0 V
FSELx = 0
FSELx = 1
Condition
t
sk(PP)
t
SK(P)
DC
Q
t
r
, t
f
1. AC characteristics apply for parallel output termination of 50
Ω
to V
TT
.
2. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
4. Output pulse skew t
SK(P)
is the absolute difference of the propagation delay times: | t
PLH
– t
PHL
|. Output duty cycle is frequency
dependent: DC
Q
= (0.5 ± t
SK(P)
•
f
OUT
). For example at f
OUT
= 125 MHz the output duty cycle limit is 50% ± 2.5%.
MPC9446
4
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 8. DC Characteristics
(V
CC
= V
CCA
= V
CCB
= V
CCC
= 2.5 V ± 5%, T
A
= –40°C to +85°C)
Symbol
V
IH
V
IL
V
OH
V
OL
Z
OUT
I
IN
I
CCQ(3)
Characteristics
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Impedance
Input Current
(2)
Maximum Quiescent Supply Current
17 – 20
(2)
±200
2.0
Min
1.7
–0.3
1.8
0.6
Typ
Max
V
CC
+ 0.3
0.7
Unit
V
V
V
V
Ω
µA
mA
V
IN
= GND or V
IN
= V
CC
All V
CC
Pins
Condition
LVCMOS
LVCMOS
I
OH
= –15 mA
(1)
I
OL
= 15 mA
1. The MPC9446 is capable of driving 50
Ω
transmission lines on the incident edge. Each output drives one 50
Ω
parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
Ω
series terminated transmission lines per
output.
2. Input pull-up / pull-down resistors influence input current.
3. I
CCQ
is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 9. AC Characteristics
(V
CC
= V
CCA
= V
CCB
= V
CCC
= 2.5 V ± 5%, T
A
= –40°C to +85°C)
(1)
Symbol
f
ref
f
MAX
t
P, REF
t
r
, t
f
t
PLH
t
PHL
t
PLZ, HZ
t
PZL, LZ
t
sk(O)
Input Frequency
Maximum Output Frequency
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation Delay
Output Disable Time
Output Enable Time
Output-to-Output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
Device-to-Device Skew
Output Pulse
Skew
(4)
÷1
or
÷2
output
45
0.1
50
CCLK0,1 to any Q
CCLK0,1 to any Q
2.6
2.6
÷1
output
÷2
output
Characteristics
Min
0
0
0
1.4
1.0
(3)
5.6
5.5
10
10
150
200
350
3.0
200
55
1.0
Typ
Max
250
(2)
250
(2)
125
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ps
ps
ps
ns
ps
%
ns
DC
REF
= 50%
0.6 to 1.8 V
0.7 to 1.7 V
FSELx = 0
FSELx = 1
Condition
t
sk(PP)
t
SK(P)
DC
Q
t
r
, t
f
Output Duty Cycle
Output Rise/Fall Time
1. AC characteristics apply for parallel output termination of 50
Ω
to V
TT
.
2. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
4. Output pulse skew t
SK(P)
is the absolute difference of the propagation delay times: | t
PLH
– t
PHL
|. Output duty cycle is frequency
dependent: DC
Q
= (0.5 ± t
SK(P)
•
f
OUT
). For example at f
OUT
= 125 MHz the output duty cycle limit is 50% ± 2.5%.
Table 10. AC Characteristics
(V
CC
= 3.3 V + 5%, V
CCA
, V
CCB
, V
CCC
= 2.5 V + 5% or 3.3 V + 5%, T
A
= –40°C to +85°C)
(1) (2)
Symbol
t
sk(O)
Characteristics
Output-to-Output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
Device-to-Device Skew
Propagation Delay
Output Pulse Skew
Output Duty Cycle
(3)
Min
Typ
Max
150
250
350
2.5
Unit
ps
ps
ps
ns
ps
%
Condition
t
sk(PP)
t
PLH,HL
t
SK(P)
DC
Q
CCLK0,1 to any Q
See 3.3 V Table
250
÷1
or
÷2
output
45
50
55
DC
REF
= 50%
1. AC characteristics apply for parallel output termination of 50
Ω
to V
TT
.
2. For all other AC specifications, refer to 2.5 V or 3.3 V tables according to the supply voltage of the output bank.
3. Output pulse skew t
SK(P)
is the absolute difference of the propagation delay times: | t
PLH
– t
PHL
|. Output duty cycle is frequency
dependent: DC
Q
= (0.5 ± t
SK(P)
•
f
OUT
).
MPC9446
Advanced Clock Drivers Devices
Freescale Semiconductor
5
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