PreliminaryData
Sheet
μ
PC3250T7L
SiGe CMOS/BiCMOS Integrated Circuit
IF Down-converter MMIC for Ku-band LNB Converter
DESCRIPTION
The
μPC3250T7L
is a CMOS/BiCMOS MMIC for Ku-band LNB converter.
This device is housed in a 24-pin plastic QFN (Quad Flat Non-Leaded) (T7L) package.
R09DS0052EJ0100
Rev.1.00
Oct 23, 2012
FEATURES
•
•
•
•
•
Low power consumption
: 3.3 V/63 mA, 208 mW
Switched LO frequency
: 9.75 G Hz, 10.6 GHz, 10.75 GHz
2 step Gain selected function : 41 dB/36 dB
Low noise figure
: 7.5 dB
Fully integrated Mixer/Oscillator/PLL synthesizer/IF Amplifier/4-channel FET bias supply circuit/
Polarity control voltage detector/Tone control signal detector
•
Integrated power save detector
•
24-pin plastic QFN (T7L) package (4.0
×
4.0
×
0.6 mm)
APPLICATIONS
•
Ku-band Low Noise Block (LNB) converters for satellite receiver (DVB-S, ABS-S application)
ORDERING INFORMATION
Order Number
Package
Marking
Supplying Form
μ
PC3250T7L-E1-A 24-pin plastic QFN C3250
•
Embossed tape 12 mm wide
(0.5 mm pitch)
•
Pin 7 to 12 face the perforation side of the tape
(Pb-Free)
•
Qty 5 kpcs/reel
•
Dry packing specification (MSL 3 Equivalent)
Remark
To order evaluation samples, please contact your nearby sales office.
Part number for sample order:
μ
PC3250T7L
Part Number
μ
PC3250T7L-E1
CAUTION
Observe precautions when handling because these devices are sensitive to electrostatic discharge.
R09DS0052EJ0100 Rev.1.00
Oct 23, 2012
Page 1 of 18
μ
PC3250T7L
PIN CONNECTIONS
(Bottom View)
6
5
4
3
2
1
Pin 1 Identifier
1
(Bottom View)
2
3
4
5
6
7
8
9
10
11
12
24
23
22
24
23
22
21
20
19
7
8
21
20
19
GND
9
10
11
12
13 14 15 16 17 18
Pin No.
1
2
3
4
5
6
Remark
Pin Name
NC
RF
in
NC
R
cal
V
DH
V
GH
NC means no connection pin.
Heat sink of bottom side of this device is connected to GND.
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Control Voltage
(TonePol, LO
sel
, G
SW
)
Power dissipation
Note
Storage Temperature
Operating Ambient Temperature
Input Power
Note:
Symbol
V
CCRF
, V
CCIF
, V
DDPLL
V
POLA
, V
LOsel
, G
SW
P
tot
T
stg
T
A
P
in
Ratings
+4.0
+4.0
1.53
−55
to +125
−40
to +85
0
Unit
V
V
mW
°C
°C
dBm
Mounted on double-sided copper-clad 50 × 50 × 0.51 mm laminated PWB, T
A
= +85°C
R09DS0052EJ0100 Rev.1.00
Oct 23, 2012
C3250
Pin No.
7
8
9
10
11
12
V
DV
18 17 16 15 14 13
Pin Name
Pin No.
13
14
15
16
17
18
Pin Name
G
SW
CVNeg
XO2
XO1
V
ref
CP
out
Pin No.
19
20
21
22
23
24
Pin Name
V
DDPLL
TonePol
IF
out
V
CCIF
V
CCRF
LO
sel
V
GV
V
D
1
V
G
1
V
D
2
V
G
2
Page 2 of 18
μ
PC3250T7L
BLOCK DIAGRAM
Top View
18
CVNeg
13
CP
out
XO2
XO1
19
V
DDPLL
G
SW
V
ref
12
V
G
2
TonePol
Tone
Polarity
XO
PDCP
Vnega
V
D
2
Bias1
Bias2
V
G
1
IF
out
IF Amp
V
CCIF
Mix
V
CCRF
Pre Amp
LO
sel
Divider
IVref
VCO
V
D
1
Bias3
V
GV
Bias4
V
DV
24
1 pin
RF
in
V
GH
R
cal
V
DH
NC
NC
7
1
6
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Remark
Name
NC
RF
in
NC
R
cal
V
DH
V
GH
V
DV
V
GV
V
D
1
V
G
1
V
D
2
V
G
2
G
SW
CVNeg
XO2
XO1
V
ref
CP
out
V
DDPLL
TonePol
IF
out
V
CCIF
V
CCRF
LO
sel
No Connection
Description
Ku band RF signal input, AC coupling required.
No Connection
LNFET drain current adjust by resister
Horizontal LNFET drain voltage supply
Horizontal LNFET gate bias voltage
Vertical LNFET drain voltage supply
Vertical LNFET gate bias voltage
Common LNFET drain voltage supply 1
Common LNFET gate bias voltage 1
Common LNFET drain voltage supply 2
Common LNFET gate bias voltage 2
Gain control input terminal
Negative voltage line decoupling
Crystal oscillator connection terminal 2
Crystal oscillator connection terminal 1
Reference voltage line decoupling
Charge pump output, connect capacitor for loop filter
PLL Power supply terminal. Decoupling capacitor required
Tone and Polarity control signal input terminal
L band IF signal output, AC coupling required
IF Power supply terminal. Decoupling capacitor required
RF Power supply terminal. Decoupling capacitor required
Local Oscillator frequency control input terminal
NC means no connection pin.
Heat sink of bottom side of this device is connected to GND.
R09DS0052EJ0100 Rev.1.00
Oct 23, 2012
Page 3 of 18
μ
PC3250T7L
RECOMMENDED OPERATING RANGE (T
A
= +25°C, unless otherwise specified)
Parameter
Supply Voltage
Symbol
V
CCRF
,
V
CCIF
,
V
DDPLL
V_
High
V_
Low
T
A
f
RF
f
IF
f
LO
MIN.
+3.0
TYP.
+3.3
MAX.
+3.6
Unit
V
High level of Control Voltage
(LO
sel
, G
SW
)
Low level of Control Voltage
(LO
sel
, G
SW
)
Operating Ambient Temperature
RF Input frequency
IF Output frequency
LO frequency
V
DD
−
0.5
0
−40
10.7
950
−
−
−
−
−
+25
−
−
9.75
10.6
10.75
22
0.6
−
−
10
V
DD
Note 1
0.5
+85
12.75
2 150
−
−
−
26
0.8
18
V
DD
18
V
V
°C
GHz
GHz
GHz
TONE control signal frequency
TONE control signal voltage
Polarity control voltage
Note 2
Input Voltage of pin 20
(TonePol)
Adjustment supply current
for each FET
Notes: 1
2
f
TONE
V
TONE
V
POLA
V
TP
I
D
18
0.4
13
0
5
kHz
Vp-p
V
V
mA
V
DD
: Supply Voltage = V
CCRF
= V
CCIF
= V
DDPLL
See the evaluation (application) circuit.
The detail connection of pin 20 (TonePol) is shown in the evaluation circuit.
This pin cannot be directly connected to 13 V/18 V polarity control voltage.
The polarity control voltage must be divided to a low voltage by the external resistors.
ELECTRICAL CHARACTERISTICS
(T
A
= +25°C, V
CCRF
= V
CCIF
= V
DDPLL
= +3.3 V, Z
S
= Z
L
= 50
Ω,
f
xtal
= 25 MHz,
unless otherwise specified)
Parameter
Total Supply Current 1
Note
(V
CCRF
, V
CCIF
, V
DDPLL
)
Normal mode
(High Gain selected)
Total Supply Current 2
Note
(V
CCRF
, V
CCIF
, V
DDPLL
)
Normal mode
(
Low Gain selected)
Total Supply Current 3
Note
(V
CCRF
, V
CCIF
, V
DDPLL
)
Power Save mode
Note:
Symbol
I
CC
1
Test Conditions
V
POLA
> 7.0 V , Non-RF input,
G
SW
= +3.3 V
(without FETs bias supply current)
V
POLA
> 7.0 V , Non-RF input,
G
SW
= 0 V
(without FETs bias supply current)
V
POLA
= 0 V ( < 3.6V)
Non-RF input
(without FETs bias supply current)
MIN.
50
TYP.
63
MAX.
80
Unit
mA
I
CC
2
48.5
61.5
78.5
mA
I
CC
3
−
5
10
mA
See the evaluation (application) circuit.
The detail connection of pin 20 (TonePol) is shown in the evaluation circuit.
This pin cannot be directly connected to 13 V/18 V polarity control voltage.
The polarity control voltage must be divided to a low voltage by the external resistors.
R09DS0052EJ0100 Rev.1.00
Oct 23, 2012
Page 4 of 18
μ
PC3250T7L
ELECTRICAL CHARACTERISTICS
(T
A
= +25°C, V
CCRF
= V
CCIF
= V
DDPLL
= +3.3 V, G
SW
= +3.3 V, Z
S
= Z
L
= 50
Ω,
f
xtal
= 25 MHz,
unless otherwise specified)
Parameter
Conversion Gain 1
Note 1
Conversion Gain 2
Note 1
Conversion Gain 3
Note 1
POLA control Threshold
Voltage 1
Note 1
POLA control Threshold
Voltage 2
Note 1
(Channel selection )
TONE control signal Threshold
Voltage
Note 1
(Channel selection)
Drain Voltage H
Note 1, 2
Drain Voltage V
Note 1, 2
Drain Voltage 1
Note 1, 2
Drain Voltage 2
Note 1, 2
Drain Current H
Note 1, 2
Drain Current V
Note 1, 2
Drain Current 1
Note 1, 2
Drain Current 2
Note 1, 2
Gate Voltage H
Note 1, 2
of FET OFF mode
Gate Voltage V
Note 1, 2
of FET OFF mode
Notes: 1
Symbol
G
conv
1
G
conv
2
G
conv
3
V
th_POLA
1
V
th_POLA
2
Test Conditions
f
LO
= 9.75 GHz, f
IF
= 1.5 GHz,
P
in
=
−50
dBm
f
LO
= 10.6 GHz, f
IF
= 1.5 GHz,
P
in
=
−50
dBm
f
LO
= 10.75 GHz, f
IF
= 1.5 GHz,
P
in
=
−50
dBm
Power Save mode to Normal mode
Dividing resistor : 8.2 kΩ/51 kΩ
Vertical mode to Horizontal mode
Dividing resistor : 8.2 kΩ/51 kΩ
Low band to High band
f
TONE
= 22 kHz, Duty Cycle = 50%,
Pulse wave
Divider capacitor : 0.1
μ
F/0.1
μ
F
V
POLA
= 18 V, I
D
= 10 mA,
R
cal
= 22 kΩ
V
POLA
= 13 V, I
D
= 10 mA,
R
cal
= 22 kΩ
I
D
= 10 mA, R
cal
= 22 kΩ
I
D
= 10 mA, R
cal
= 22 kΩ
V
POLA
= 18 V, R
cal
= 22 kΩ
V
POLA
= 13 V, R
cal
= 22 kΩ
R
cal
= 22 kΩ
R
cal
= 22 kΩ
V
POLA
= 13 V
V
POLA
= 18 V
MIN.
37
37
37
3.6
15.2
TYP.
41
41
41
−
15.7
MAX.
45
45
45
7.0
16.2
Unit
dB
dB
dB
V
V
V
th_TONE
0.1
0.15
0.35
V
p-p
V
DH
V
DV
V
D
1
V
D
2
I
DH
I
DV
I
D
1
I
D
2
V
GH
V
GV
1.8
1.8
1.8
1.8
8.5
8.5
8.5
8.5
−2.0
−2.0
2.0
2.0
2.0
2.0
10
10
10
10
−2.5
−2.5
2.2
2.2
2.2
2.2
11.5
11.5
11.5
11.5
−3.0
−3.0
V
V
V
V
mA
mA
mA
mA
V
V
2
See the evaluation (application) circuit.
The detail connection of pin 20 (TonePol) is shown in the evaluation circuit.
This pin cannot be directly connected to 13 V/18 V polarity control voltage.
The polarity control voltage must be divided to a low voltage by the external resistors.
See the graph of “R
cal
vs. I
DFET
, V
DFET
.” FET’s drain current can be adjusted by the external resisters (R
cal
).
R09DS0052EJ0100 Rev.1.00
Oct 23, 2012
Page 5 of 18
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