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MT58L256L18F1T-7.5IT

Description
Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100
Categorystorage    storage   
File Size631KB,31 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT58L256L18F1T-7.5IT Overview

Cache SRAM, 256KX18, 7.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

MT58L256L18F1T-7.5IT Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicron Technology
Objectid1504585924
Parts packaging codeQFP
package instructionPLASTIC, MS-026BHA, TQFP-100
Contacts100
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.A
compound_id9939205
Maximum access time7.5 ns
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density4718592 bit
Memory IC TypeCACHE SRAM
memory width18
Number of functions1
Number of terminals100
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.01 A
Minimum standby current3.14 V
Maximum slew rate0.375 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
width14 mm
PRELIMINARY
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH SYNCBURST SRAM
4Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
DD
)
• Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion
and address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• 165-pin FBGA package
• 100-pin TQFP package
• 119-pin BGA package
• Low capacitive bus loading
• x18, x32, and x36 versions available
MT58L256L18F1, MT58L128L32F1,
MT58L128L36F1; MT58L256V18F1,
MT58L128V32F1, MT58L128V36F1
3.3V V
DD
, 3.3V or 2.5V I/O, Flow-Through
100-Pin TQFP
1
165-Pin FBGA
(Preliminary Package Data)
OPTIONS
• Timing (Access/Cycle/MHz)
6.8ns/7.5ns/133 MHz
7.5ns/8.8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
• Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
256K x 18
128K x 32
128K x 36
• Packages
100-pin TQFP
165-pin FBGA
119-pin, 14mm x 22mm BGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
Part Number Example:
MARKING*
-6.8
-7.5
-8.5
-10
MT58L256L18F1
MT58L128L32F1
MT58L128L36F1
MT58L256V18F1
MT58L128V32F1
MT58L128V36F1
T
F
B
None
IT
119-Pin BGA
2
MT58L256L18F1T-8.5
* A Part Marking Guide for the FBGA devices can be found on Micron’s
web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_C.p65 – Rev. 6/01
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-standard MS-028 BHA (PBGA).
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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