PL560-xx VCXO Family
PRODUCT DESCRIPTION
PhaseLink’s Analog Frequency Multiplier
TM
(AFM) is
the industry’s first ‘Balanced Oscillator’ utilizing
analog multiplication of the fundamental frequency
(at double or quadruple frequency), combined with
an attenuation of the fundamental of the reference
crystal, without the use of a phase-locked loop
(PLL), in CMOS technology.
PhaseLink’s patent pending PL560-xx family of AFM
products can achieve up to 800 MHz output
frequency with little jitter or phase noise
deterioration. In addition, the low frequency input
crystal requirement makes the AFMs the most
affordable high-performance timing-source in the
market.
PL560-xx family of products utilize low-power CMOS
technology and are housed in
Green
/
RoHS
compliant
16-pin TSSOP, and 16-pin 3x3 QFN
packages.
FEATURES
Non-PLL frequency multiplication
Input frequency from 30-200 MHz
Output frequency from 60-800 MHz
Low phase noise and jitter (equivalent to fundamental
crystal at the output frequency)
Ultra-low jitter
o
RMS phase jitter < 0.25 ps (12kHz-20MHz)
o
RMS period jitter < 2.5 ps
Low phase noise
o
-142 dBc/Hz @100kHz offset from 155.52 MHz
o
-150 dBc/Hz @10MHz offset from 155.52 MHz
High linearity pull range (typ. 5%)
+/- 120 PPM pullability VCXO
Low input frequency eliminates the need for expensive
crystals
Differential output levels (PECL, LVDS), or single-
ended CMOS
Single 3.3V, ±10% power supply
Optional industrial temperature range (-40C to +85C)
Available in 16-pin
Green/RoHS
compliant
TSSOP, and
3x3 QFN packages
Figure 1: 2x AFM Phase Noise at 311.04MHz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 10/7/2008 Page 1
PL560-xx VCXO Family
L2X
OE
X IN
O s c illa to r
A m p lifie r
F re q u e n c y
X2
F re q u e n c y
X4
VCON
QBAR
Q
XOUT
O n ly r e q u ir e d in x 4 d e s ig n s
L4X
Figure 2: Block Diagram of VCXO AFM
Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 311.04 MHz, while Figure 4
shows the very low rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.
Figure 3: Period Jitter Histogram at 311.04 MHz
Analog Frequency Multiplier (2x)
with 155.52MHz crystal
Figure 4: Spectrum Analysis at 311.04 MHz
Analog Frequency Multiplier (2x)
with sub-harmonics below –72 dBc
OE LOGIC SELECTION
OUTPUT
OESEL
0 (Default)
LVPECL
1
0 (Default)
LVDS or LVCMOS
1
OE
0 (Default)
1
0
1 (Default)
0
1 (Default)
0 (Default)
1
Output State
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
Enabled
Tri-state
OESEL and OE: Connect to VDD or leave floating to set to “1”, connect to GND to set to “0”.
Internally set to default through pull-down / -up.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 10/7/2008 Page 2
PL560-xx VCXO Family
PRODUCT SELECTION GUIDE
FREQUENCY VERSUS PHASE NOISE PERFORMANCE
Part
Number
Input
Frequency
Range
(MHz)
75 - 200
75 - 200
30 - 80
30 - 80
30 - 80
30 - 80
30 - 80
30 - 80
75 - 200
75 - 200
Analog
Frequency
Multiplication
Factor
4
4
4
4
4
2
2
2
2
2
Output
Frequency
Range
(MHz)
300 - 800
300 - 800
120 - 320
120 - 320
120 - 320
60 - 160
60 - 160
60 - 160
150 - 400
150 - 400
Phase Noise at Frequency Offset From Carrier (dBc/Hz)
Output
Type
Carrier
Freq.
(MHz)
622.08
622.08
155.52
155.52
155.52
155.52
155.52
155.52
311.04
311.04
10Hz
-55
-55
-50
-50
-50
-65
-65
-65
-60
-60
100Hz
-85
-85
-82
-82
-82
-95
-95
-95
-85
-85
1kHz
-110
-110
-110
-110
-110
-122
-122
-122
-112
-112
10kHz
-130
-130
-128
-128
-128
-138
-138
-138
-135
-135
100kHz
-137
-137
-142
-142
-142
-142
-142
-142
-142
-142
1MHz
-148
-148
-148
-148
-148
-148
-148
-148
-150
-150
10MHz
-150
-150
-150
-150
-150
-149
-149
-149
-151
-151
PL560-08
PL560-09
PL560-37
PL560-38
PL560-39
PL560-47
PL560-48
PL560-49
PL560-68
PL560-69
LVPECL
LVDS
LVCMOS
LVPECL
LVDS
LVCMOS
LVPECL
LVDS
LVPECL
LVDS
Phase noise was measured using Agilent E5500.
FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE
Part
Number
Peak to Peak
RMS
RMS Phase Jitter
Period Jitter
Accumulated 12kHz to 20MHz Spectral Specifications / Sub-harmonic Content (dBc),
Output
(ps)
(L.T.) Jitter (ps)
(ps)
Frequency (MHz)
Freq.
Carrier @
@
@
@
@
@
(MHz)
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Freq. -75% -50% -25% +25% +50% +75%
(Fc)
(Fc)
(Fc)
(Fc)
(Fc)
(Fc)
(Fc)
622
622
155
155
155
155
155
155
311
311
4
4
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
6
6
3
3
3
3
3
3
3
3
25
25
18
18
18
18
18
18
18
18
30
30
20
20
20
20
20
20
20
20
6
6
3
3
3
3
3
3
3
3
0.09
0.09
0.25
0.25
0.25
0.25
0.25
0.27
0.18
0.18
622
622
155.52
155.52
155.52
155.52
155.52
155.52
311.04
311.04
-50
-50
-75
-75
-75
-50
-50
-62
-62
-62
-68
-68
-68
-72
-72
-45
-45
-47
-47
-47
-47
-65
-65
-65
-68
-68
-68
-85
-85
-55
-55
-75
-75
-75
RMS
Period Jitter
(ps)
PL560-08
PL560-09
PL560-37
PL560-38
PL560-39
PL560-47
PL560-48
PL560-49
PL560-68
PL560-69
Note:
Wavecrest data 10,000 hits. No filtering was used in jitter calculations.
Agilent 5500 was used for phase jitter measurements.
Spectral specifications were obtained using Agilent E7401A.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 10/7/2008 Page 3
PL560-xx VCXO Family
CRYSTAL SPECIFICATIONS AND BOARD LAYOUT CONSIDERATIONS
BOARD LAYOUT CONSIDERATIONS
AFM IC
XTAL
XIN (Pin # 4)
XOUT (Pin # 5)
AFM IC
XTAL
Ceramic
SMD
XIN (Pin # 4)
XOUT (Pin # 5)
To minimize parasitic effects, and improve performance:
Place the crystal as close as possible to the IC.
Make the board traces that are connected to the crystal pins symmetrical.
The board trace symmetry is important, as it reduces the negative parasitic effects to produce a clean
frequency multiplication with low jitter. Parasitic effects reduce frequency pulling of the VCXO and
increase jitter.
CRYSTAL SPECIFICATIONS & TUNING PERFORMANCE
CRYSTAL SPECIFICATIONS
PART
NUMBER
CRYSTAL
CL (xtal)
RESONATOR
MODE
FREQUENCY
CONDI-
TYP
(FXIN)
TIONS
5pF
TUNING PERFORMANCE
ESR
(R
E
)
MAX
CRYSTAL
CRYSTAL
FREQ (MHz)
155.52
C0
3.0pF
1.8pF
2.8pF
4.5pF
5.1pF
5.3pF
2.0pF
C1
12.2fF
5.7fF
12.4fF
19.1fF
20.9fF
25.6fF
6.7fF
C0/C1
245
316
228
236
242
207
305
TUNING (Typical)
VC:
1.65V
0V
-145 ppm
-134 ppm
-167ppm
-163 ppm
-131 ppm
-157 ppm
-92 ppm
VC:
1.65V 3.3V
+108 ppm
+87 ppm
+176 ppm
+167 ppm
+98 ppm
+141 ppm
+110 ppm
At
PL560-08/09
Funda-
75 to 200MHz
VCON =
PL560-68/69
mental
1.65V
30Ω
155.52
30.72
PL560-
37/38/39
30 to 80MHz
PL560-
47/48/49
30.72
At
Funda-
VCON =
mental
1.65V
5pF
30Ω
38.88
38.88
77.76
Note:
Non specified parameters can be chosen as standard values from crystal suppliers.
CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 10/7/2008 Page 4
PL560-xx VCXO Family
VOLTAGE CONTROL SPECIFICATION
PARAMETERS
VCXO Stabilization Time
VCXO Tuning Range
CLK Output Pullability
Linearity
VCON Input Impedance
VCON Modulation BW
0V < VCON < 3.3V, -3dB
130
16
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
XTAL C
0
/C
1
<300
VCON= 1.65V,
1.65V
XTAL C
0
/C
1
<300
200
100
120
5
10
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
%
kΩ
kHz
EXTERNAL COMPONENT VALUES
INDUCTOR VALUE OPTIMIZATION
The required inductor value(s) for the best performance depends on the operating frequency, and the board
layout specifications. The listed values in this datasheet are based on the calculated parasitic values from
PhaseLink’s evaluation board design. These inductor values provide the user with a starting point to determine
the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution.
The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed
between L2X / L4X and adjacent VDDOSC pin. Place inductor as close to the IC as possible to minimize parasitic
effects and to maintain inductor Q.
To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software.
You can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two
worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second
worksheet (named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value.
For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to
determine the optimum values for the required inductors. This software is developed based on the parasitic
information from PhaseLink’s board layout and can be used to determine the required inductor and parallel
capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their
design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor
values. Please use the following fine tuning procedure:
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev. 10/7/2008 Page 5
京公网安备 11010802033920号
EEWORLD
