HIGH-SPEED 2K x 8
DUAL-PORT STATIC RAM
WITH INTERRUPTS
Integrated Device Technology, Inc.
IDT71321SA/LA
IDT71421SA/LA
FEATURES:
• High-speed access
—Commercial: 20/25/35/45/55ns (max.)
• Low-power operation
—IDT71321/IDT71421SA
—Active:
550mW (typ.)
—Standby:
5mW (typ.)
—IDT71321/421LA
—Active:
550mW (typ.)
—Standby:
1mW (typ.)
• Two
INT
flags for port-to-port communications
• MASTER IDT71321 easily expands data bus width to 16-
or-more-bits using SLAVE IDT71421
• On-chip port arbitration logic (IDT71321 only)
•
BUSY
output flag on IDT71321;
BUSY
input on IDT71421
• Fully asynchronous operation from either port
• Battery backup operation —2V data retention (LA Only)
• TTL-compatible, single 5V
±10%
power supply
• Available in popular hermetic and plastic packages
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-
Port Static RAMs with internal interrupt logic for interproces-
sor communications. The IDT71321 is designed to be used
as a stand-alone 8-bit Dual-Port RAM or as a "MASTER"
Dual-Port RAM together with the IDT71421 "SLAVE" Dual-
Port in 16-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-or-more-
bit memory system applications results in full speed, error-
free operation without the need for additional discrete logic.
Both devices provide two independent ports with sepa-
rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE
, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CMOS high-performance technol-
ogy, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum-
ing 200µW from a 2V battery.
The IDT71321/IDT71421 devices are packaged in a 52-
pin PLCC, a 64-pin TQFP, and a 64-pin STQFP.
FUNCTIONAL BLOCK DIAGRAM
OE
L
R/
OE
R
R/
CE
L
W
L
CE
R
W
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
11
(1,2)
A
10L
A
0L
MEMORY
ARRAY
Address
Decoder
A
10R
A
0R
11
NOTES:
1. IDT71321 (MASTER):
BUSY
is open drain output and
requires pullup resistor of 270Ω.
IDT71421 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup
resistor of 270Ω.
INT
L
OE
L
R/
CE
L
W
L
ARBITRATION
and
INTERRUPT
LOGIC
OE
R
R/
CE
R
W
R
(2)
INT
R
(2)
2691 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2691/6
6.03
1
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
(1,2)
BUSY
L
BUSY
R
W
R
R/
W
L
INT
R
N/C
N/C
A
10L
V
CC
CE
R
R/W
R
BUSY
R
INT
R
A
10L
INT
L
BUSY
L
R/W
L
CE
L
NDEX
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
A
10R
A
0L
OE
L
INDEX
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
2691 drw 02
87 6
9
10
11
12
13
14
15
16
17
18
19
20
21
5 4
3 2
1
52 51 50 49 48 47
46
45
44
43
NC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
4L
I/O
5L
I/O
6L
I/O
7L
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
42
IDT71321/421
41
J52-1
40
PLCC
TOP VIEW
(3)
39
38
37
36
35
34
22 23 24 25 26 27 28 29 30 31 32 33
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
N/C
A
7L
A
8L
A
9L
N/C
I/O
0L
I/O
1L
I/O
2L
OE
L
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
V
CC
V
CC
CE
R
A
10R
N/C
N/C
INT
L
R/
CE
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IDT71321/421
PN64-1 / PP64-1
64-PIN TQFP
64-PIN STQFP
TOP VIEW
(3)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
N/C
A
7R
A
8R
A
9R
N/C
N/C
I/O
7R
I/O
6R
2691 drw 03
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect to
GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
–0.5 to +7.0
Unit
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient
Temperature
0°C to +70°C
GND
0V
V
CC
5.0V
±
10%
2691 tbl 02
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to +125
50
°C
°C
°C
mA
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
Typ.
5.0
0
—
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2691 tbl 03
2691 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of the specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM >
Vcc + 0.5V.
NOTES:
1. V
IL
(min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
CAPACITANCE
(1,3)
(T
A
= +25°C, f = 1.0MHz) TQFP ONLY
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
IN
= 3dV
Max. Unit
9
pF
10
pF
2691 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
3. 11pF max. for other packages.
6.03
I/O
3L
N/C
I/O
4L
I/O
5L
I/O
6L
I/O
7L
N/C
GND
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
N/C
I/O
4R
I/O
5R
–0.5
(1)
—
2
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1,4)
(V
CC
= 5.0V
±
10%)
71321X25 71321X35 71321X55 71321X100
71421X25 71421X35 71421X55 71421X100
Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
—
— 110 280
—
— 110 220
110 250 110 220
110 200 110 170
—
—
30
30
—
—
65
65
—
—
1.0
0.2
—
—
60
60
—
—
65
45
—
—
165
125
—
—
15
5
—
—
155
115
30
30
30
30
65
65
65
65
1.0
0.2
1.0
0.2
60
60
60
60
80
60
65
45
160
125
150
115
30
10
15
5
155
115
145
105
80
80
80
80
25
25
25
25
50
50
50
50
1.0
0.2
1.0
0.2
45
45
45
45
230
170
165
120
80
60
65
45
150
115
125
90
30
10
15
4
145
105
110
85
65
65
65
65
20
20
20
20
190
140
155
110
65
45
65
35
65
65
65
65
20
20
20
20
40
40
40
40
1.0
0.2
1.0
0.2
40
40
40
40
190
140
155
110
65
45
55
35
125
90
110
75
30
10
15
4
110
80
95
70
mA
71321X20
Symbol
I
CC
Parameter
Dynamic Operating
Current (Both Ports
Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Test Conditions
CE
L
Version
MIL.
SA
LA
COM'L. SA
LA
and
CE
R
= V
IL
,
Outputs open,
f = f
MAX
(2)
I
SB1
CE
L
and
CE
R
= V
IH
, MIL.
(2)
f = f
MAX
SA
LA
COM'L. SA
LA
MIL.
SA
LA
COM'L. SA
LA
mA
I
SB2
V
IL
and
(5)
CE
"
B
"
=
V
IH
Active Port Outputs
Open, f = f
MAX
(2)
CE
"
A
"
=
40 125
40 90
40 110
40 75
1.0
0.2
1.0
0.2
30
10
15
4
mA
I
SB3
Full Standby Current
CE
L
and
(Both Ports - All
CE
R
> V
CC
-0.2V,
CMOS Level Inputs V
IN
> V
CC
-0.2V or
V
IN
< 0.2V,f = 0
(3)
SA
LA
COM'L. SA
LA
MIL.
mA
I
SB4
Full Standby Current
CE
"
A
"
<
0.2V and
MIL.
SA
(5)
(One Port - All
CE
"
B
"
> V
CC
-0.2V
LA
CMOS Level Inputs) V
IN
> V
CC
-0.2V or COM'L. SA
V
IN
< 0.2V,
LA
Active Port Outputs
Open, f = f
MAX
(2)
40 110
40 85
40 100
40 70
mA
NOTES:
2689 tbl 05
1. 'X' in part numbers indicates power rating (SA or LA).
2. At f = f
Max
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC TEST CONDITIONS”
of input levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, T
A
=+25°C for Typ. and is not production tested. Vcc
DC
= 100mA (Typ)
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 5.0V
±
10%)
Symbol
|l
Ll
|
|l
LO
|
V
OL
V
OL
V
OH
Parameter
Input Leakage
Current
(1)
Output Leakage
Current
(1)
Output Low Voltage
(l/O
0
-l/O
7
)
Open Drain Output Low
Voltage (
BUSY
,
INT
)
Output High Voltage
Test Conditions
V
CC
= 5.5V,
V
IN
= 0V to V
CC
V
IN
= GND to V
CC
CE
IDT71321SA
IDT71421SA
Min.
Max.
—
10
10
0.4
0.5
—
lDT71321LA
lDT71421LA
Min.
Max.
—
—
—
—
2.4
5
5
0.4
0.5
—
Unit
µA
µA
V
V
V
2691 tbl 06
= V
IH
, V
OUT
= 0V to V
CC
—
V
CC
= 5.5V
C-=S
= V
IH
, V
OUT
= GND to V
CC
—
—
2.4
l
OL
= 4mA
l
OL
= 16mA
l
OL
= 16mA
l
OH
= -4mA
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Supply CurrentV
IN
> V
CC
-0.2V or < 0.
6.03
3
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS
(LA Version Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery
Time
Test Conditions
V
CC
= 2.0V,
CE
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
≤
0.2V
COM'L.
71321LA/71421LA
Max.
Min.
Typ.
(1)
2.0
—
0
t
RC
(2)
—
100
—
—
0
1500
—
—
Unit
V
µA
ns
ns
2691 tbl 07
(3)
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and is not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed by device characterization but not production tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1, 2, and 3
2691 tbl 08
V
CC
4.5V
t
CDR
V
DR
≥
2.0V
4.5V
t
R
CE
V
DR
V
IH
V
IH
2691 drw 04
5V
1250Ω
DATA
OUT
775Ω
30pF
100pF for 55 and 100ns versions
5V
1250Ω
DATA
OUT
775Ω
5pF
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for t
HZ
, t
LZ
, t
WZ
, and t
OW
)
* Including scope and jig.
5V
270Ω
2691 drw 05
BUSY
or
INT
30pF
100pF for 55 and 100ns versions
Figure 3.
BUSY
and I
NT
AC Output Test Load
6.03
4
IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(2)
Symbol
Read Cycle
t
RC
t
AA
t
ACE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time
(1,3)
Output High-Z Time
(1,3)
Chip Enable to Power Up Time
(3)
Chip Disable to Power Down Time
(3)
20
—
—
3
0
—
0
—
—
20
20
11
—
—
10
—
20
25
—
—
—
3
0
—
0
—
—
25
25
12
—
—
10
—
25
35
—
—
—
3
0
—
0
—
—
35
35
20
—
—
15
—
35
55
—
—
—
3
5
—
0
—
—
55
55
25
—
—
25
—
50
100
—
—
—
10
5
—
0
—
—
100
100
40
—
—
40
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
2689 tbl 09
Parameter
71321X25 71321X35 71321X55 71321X100
71421X25 71421X35 71421X55 71421X100
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
71321X20
NOTES:
1. Transition is measured
±500mV
from Low or High-impedance voltage Output Test Load (Figure 2).
2. “X” in part numbers indicates power rating (SA or LA).
3. This parameter is guaranteed by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(1)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
t
OH
BUSY
OUT
t
BDDH
(2,3)
2691 drw 06
NOTES:
1. R/
W
= V
IH
,
CE
= V
IL
, and
OE
= V
IL
. Address is valid prior to or coincidental with
CE
transition Low.
2. t
BDD
delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read
operations
BUSY
has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
, t
AA
, and t
BDD
.
6.03
5
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